JP5207336B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5207336B2
JP5207336B2 JP2006155658A JP2006155658A JP5207336B2 JP 5207336 B2 JP5207336 B2 JP 5207336B2 JP 2006155658 A JP2006155658 A JP 2006155658A JP 2006155658 A JP2006155658 A JP 2006155658A JP 5207336 B2 JP5207336 B2 JP 5207336B2
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JP
Japan
Prior art keywords
semiconductor chip
spacer
sides
electrode pads
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006155658A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007324506A5 (https=
JP2007324506A (ja
Inventor
宏 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2006155658A priority Critical patent/JP5207336B2/ja
Priority to US11/756,941 priority patent/US7777347B2/en
Publication of JP2007324506A publication Critical patent/JP2007324506A/ja
Publication of JP2007324506A5 publication Critical patent/JP2007324506A5/ja
Application granted granted Critical
Publication of JP5207336B2 publication Critical patent/JP5207336B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5366—Shapes of wire connectors the bond wires having kinks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2006155658A 2006-06-05 2006-06-05 半導体装置 Expired - Fee Related JP5207336B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006155658A JP5207336B2 (ja) 2006-06-05 2006-06-05 半導体装置
US11/756,941 US7777347B2 (en) 2006-06-05 2007-06-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006155658A JP5207336B2 (ja) 2006-06-05 2006-06-05 半導体装置

Publications (3)

Publication Number Publication Date
JP2007324506A JP2007324506A (ja) 2007-12-13
JP2007324506A5 JP2007324506A5 (https=) 2009-07-09
JP5207336B2 true JP5207336B2 (ja) 2013-06-12

Family

ID=38789180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006155658A Expired - Fee Related JP5207336B2 (ja) 2006-06-05 2006-06-05 半導体装置

Country Status (2)

Country Link
US (1) US7777347B2 (https=)
JP (1) JP5207336B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8427891B2 (en) * 2007-04-17 2013-04-23 Rambus Inc. Hybrid volatile and non-volatile memory device with a shared interface circuit
JP5183186B2 (ja) * 2007-12-14 2013-04-17 ルネサスエレクトロニクス株式会社 半導体装置
CN103098206A (zh) * 2010-03-18 2013-05-08 莫塞德技术公司 具有偏移裸片叠层的多芯片封装及其制造方法
JP2017078958A (ja) * 2015-10-20 2017-04-27 株式会社東芝 半導体装置
US11195820B2 (en) * 2020-03-03 2021-12-07 Sandisk Technologies Llc Semiconductor device including fractured semiconductor dies

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
DE10142120A1 (de) * 2001-08-30 2003-03-27 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung
JP4076841B2 (ja) * 2002-11-07 2008-04-16 シャープ株式会社 半導体装置の製造方法
JP4068974B2 (ja) * 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
KR100621547B1 (ko) * 2004-01-13 2006-09-14 삼성전자주식회사 멀티칩 패키지
US7378725B2 (en) * 2004-03-31 2008-05-27 Intel Corporation Semiconducting device with stacked dice
JP2005322767A (ja) 2004-05-10 2005-11-17 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP4188337B2 (ja) * 2004-05-20 2008-11-26 株式会社東芝 積層型電子部品の製造方法
JP4215689B2 (ja) * 2004-06-17 2009-01-28 株式会社新川 ワイヤボンディング方法及びバンプ形成方法
JP2006066816A (ja) * 2004-08-30 2006-03-09 Toshiba Corp 半導体装置の製造方法及び半導体装置
US20070001296A1 (en) * 2005-05-31 2007-01-04 Stats Chippac Ltd. Bump for overhang device
US7229928B2 (en) * 2005-08-31 2007-06-12 Infineon Technologies Ag Method for processing a layered stack in the production of a semiconductor device

Also Published As

Publication number Publication date
US20070278697A1 (en) 2007-12-06
JP2007324506A (ja) 2007-12-13
US7777347B2 (en) 2010-08-17

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