JP5185885B2 - 配線基板および半導体装置 - Google Patents

配線基板および半導体装置 Download PDF

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Publication number
JP5185885B2
JP5185885B2 JP2009123040A JP2009123040A JP5185885B2 JP 5185885 B2 JP5185885 B2 JP 5185885B2 JP 2009123040 A JP2009123040 A JP 2009123040A JP 2009123040 A JP2009123040 A JP 2009123040A JP 5185885 B2 JP5185885 B2 JP 5185885B2
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Japan
Prior art keywords
wiring board
solder mask
opening
connection pad
center
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009123040A
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English (en)
Japanese (ja)
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JP2010272681A (ja
JP2010272681A5 (https=
Inventor
隆史 小澤
聖二 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009123040A priority Critical patent/JP5185885B2/ja
Priority to US12/782,054 priority patent/US8232641B2/en
Publication of JP2010272681A publication Critical patent/JP2010272681A/ja
Publication of JP2010272681A5 publication Critical patent/JP2010272681A5/ja
Application granted granted Critical
Publication of JP5185885B2 publication Critical patent/JP5185885B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2009123040A 2009-05-21 2009-05-21 配線基板および半導体装置 Active JP5185885B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009123040A JP5185885B2 (ja) 2009-05-21 2009-05-21 配線基板および半導体装置
US12/782,054 US8232641B2 (en) 2009-05-21 2010-05-18 Wiring substrate and semiconductor device having connection pads formed in non-solder mask defined structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009123040A JP5185885B2 (ja) 2009-05-21 2009-05-21 配線基板および半導体装置

Publications (3)

Publication Number Publication Date
JP2010272681A JP2010272681A (ja) 2010-12-02
JP2010272681A5 JP2010272681A5 (https=) 2012-04-12
JP5185885B2 true JP5185885B2 (ja) 2013-04-17

Family

ID=43124047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009123040A Active JP5185885B2 (ja) 2009-05-21 2009-05-21 配線基板および半導体装置

Country Status (2)

Country Link
US (1) US8232641B2 (https=)
JP (1) JP5185885B2 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032337A1 (en) * 2010-08-06 2012-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Flip Chip Substrate Package Assembly and Process for Making Same
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
JP2013093538A (ja) * 2011-10-04 2013-05-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
CN103096618B (zh) * 2011-10-31 2016-03-30 联发科技（新加坡）私人有限公司 印刷电路板以及电子设备
US8927878B2 (en) * 2011-10-31 2015-01-06 Mediatek Singapore Pte. Ltd Printed circuit board and electronic apparatus thereof
TWI473230B (zh) * 2011-11-29 2015-02-11 力成科技股份有限公司 可光學檢測銲罩開口偏移在容許範圍內之封裝基板
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
CN103681358B (zh) * 2012-08-31 2017-06-06 碁鼎科技秦皇岛有限公司 芯片封装基板和结构及其制作方法
JP6207190B2 (ja) * 2013-03-22 2017-10-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
TW201503777A (zh) * 2013-05-30 2015-01-16 京瓷Ｓｌｃ技術股份有限公司 配線基板
US9831205B2 (en) * 2013-11-18 2017-11-28 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
JP6352644B2 (ja) * 2014-02-12 2018-07-04 新光電気工業株式会社 配線基板及び半導体パッケージの製造方法
US9721880B2 (en) * 2015-12-15 2017-08-01 Intel Corporation Integrated circuit package structures
JP6251828B2 (ja) * 2017-01-30 2017-12-20 ルネサスエレクトロニクス株式会社 半導体装置
US11652037B2 (en) * 2020-07-31 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacture
JP7519248B2 (ja) 2020-09-18 2024-07-19 新光電気工業株式会社 配線基板及びその製造方法
US11804428B2 (en) * 2020-11-13 2023-10-31 Qualcomm Incorporated Mixed pad size and pad design
JP7841689B2 (ja) 2022-03-17 2026-04-07 新光電気工業株式会社 配線基板及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3865989B2 (ja) * 2000-01-13 2007-01-10 新光電気工業株式会社 多層配線基板、配線基板、多層配線基板の製造方法、配線基板の製造方法、及び半導体装置
TWI241702B (en) * 2003-07-28 2005-10-11 Siliconware Precision Industries Co Ltd Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure
JP2007158081A (ja) 2005-12-06 2007-06-21 Shinko Electric Ind Co Ltd 実装基板および半導体装置
JP4971769B2 (ja) * 2005-12-22 2012-07-11 新光電気工業株式会社 フリップチップ実装構造及びフリップチップ実装構造の製造方法
JP5091469B2 (ja) * 2006-12-05 2012-12-05 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
JP4956173B2 (ja) * 2006-12-19 2012-06-20 新光電気工業株式会社 フリップチップ実装用基板
KR100816762B1 (ko) * 2007-01-02 2008-03-25 삼성전자주식회사 반도체 패키지 및 이를 탑재하기 위한 모듈 인쇄회로기판
US7772104B2 (en) * 2007-02-02 2010-08-10 Freescale Semiconductor, Inc. Dynamic pad size to reduce solder fatigue

Also Published As

Publication number Publication date
JP2010272681A (ja) 2010-12-02
US20100295174A1 (en) 2010-11-25
US8232641B2 (en) 2012-07-31

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