JP5184132B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

Info

Publication number
JP5184132B2
JP5184132B2 JP2008034089A JP2008034089A JP5184132B2 JP 5184132 B2 JP5184132 B2 JP 5184132B2 JP 2008034089 A JP2008034089 A JP 2008034089A JP 2008034089 A JP2008034089 A JP 2008034089A JP 5184132 B2 JP5184132 B2 JP 5184132B2
Authority
JP
Japan
Prior art keywords
chip
pad electrode
main surface
spacer
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008034089A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009194189A5 (enrdf_load_html_response
JP2009194189A (ja
Inventor
誠 荒木
強 宮崎
修康 武藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2008034089A priority Critical patent/JP5184132B2/ja
Publication of JP2009194189A publication Critical patent/JP2009194189A/ja
Publication of JP2009194189A5 publication Critical patent/JP2009194189A5/ja
Application granted granted Critical
Publication of JP5184132B2 publication Critical patent/JP5184132B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2008034089A 2008-02-15 2008-02-15 半導体装置およびその製造方法 Expired - Fee Related JP5184132B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008034089A JP5184132B2 (ja) 2008-02-15 2008-02-15 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008034089A JP5184132B2 (ja) 2008-02-15 2008-02-15 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2009194189A JP2009194189A (ja) 2009-08-27
JP2009194189A5 JP2009194189A5 (enrdf_load_html_response) 2011-02-10
JP5184132B2 true JP5184132B2 (ja) 2013-04-17

Family

ID=41075942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008034089A Expired - Fee Related JP5184132B2 (ja) 2008-02-15 2008-02-15 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JP5184132B2 (enrdf_load_html_response)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10784244B2 (en) 2018-02-20 2020-09-22 Samsung Electronics Co., Ltd. Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5673423B2 (ja) 2011-08-03 2015-02-18 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法
JP2013093483A (ja) * 2011-10-27 2013-05-16 Semiconductor Components Industries Llc 半導体装置及びその製造方法
JP2016048756A (ja) 2014-08-28 2016-04-07 マイクロン テクノロジー， インク． 半導体装置
KR102185706B1 (ko) * 2017-11-08 2020-12-02 삼성전자주식회사 팬-아웃 반도체 패키지
US10643919B2 (en) 2017-11-08 2020-05-05 Samsung Electronics Co., Ltd. Fan-out semiconductor package
CN110444528B (zh) * 2018-05-04 2021-04-20 晟碟信息科技（上海）有限公司 包含虚设下拉式引线键合体的半导体装置
CN116314114B (zh) * 2023-05-24 2023-08-04 遂宁合芯半导体有限公司 一种半导体封装结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030018204A (ko) * 2001-08-27 2003-03-06 삼성전자주식회사 스페이서를 갖는 멀티 칩 패키지
JP2005197491A (ja) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd 半導体装置
JP4494240B2 (ja) * 2005-02-03 2010-06-30 富士通マイクロエレクトロニクス株式会社 樹脂封止型半導体装置
JP5205867B2 (ja) * 2007-08-27 2013-06-05 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5529371B2 (ja) * 2007-10-16 2014-06-25 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10784244B2 (en) 2018-02-20 2020-09-22 Samsung Electronics Co., Ltd. Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package

Also Published As

Publication number Publication date
JP2009194189A (ja) 2009-08-27

Similar Documents

Publication Publication Date Title
JP5529371B2 (ja) 半導体装置及びその製造方法
US8786102B2 (en) Semiconductor device and method of manufacturing the same
US8076770B2 (en) Semiconductor device including a first land on the wiring substrate and a second land on the sealing portion
JP3839323B2 (ja) 半導体装置の製造方法
US7944049B2 (en) Semiconductor device and manufacturing method thereof
JP5570799B2 (ja) 半導体装置及びその製造方法
JP5184132B2 (ja) 半導体装置およびその製造方法
US9570405B2 (en) Semiconductor device and method for manufacturing same
JP2009124151A (ja) 接合信頼性の向上した積層型半導体パッケージ
WO2014042165A1 (ja) 半導体装置および半導体装置の製造方法
JP2010147070A (ja) 半導体装置
KR20150060758A (ko) 반도체 장치 및 그 제조방법
JP2012230981A (ja) 半導体装置及びその製造方法
US20110316150A1 (en) Semiconductor package and method for manufacturing semiconductor package
JP5557439B2 (ja) 半導体装置及びその製造方法
JP5619381B2 (ja) 半導体装置及び半導体装置の製造方法
CN102044528A (zh) 层叠封装件及其制造方法
WO2014203739A1 (ja) 半導体装置及びその製造方法
JP2012054496A (ja) 半導体装置および半導体装置の製造方法
JP5621712B2 (ja) 半導体チップ
JP2005142452A (ja) 半導体装置及びその製造方法
JP5666211B2 (ja) 配線基板及び半導体装置の製造方法
JP2013157433A (ja) 半導体装置
JP2012099693A (ja) 半導体装置の製造方法
US20150333041A1 (en) Semiconductor device and manufacturing method therefor

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100528

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101222

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101222

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111209

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121225

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130116

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160125

Year of fee payment: 3

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees