JP5181261B2 - 集積回路のためのコンタクトパッドおよびコンタクトパッドの形成方法 - Google Patents

集積回路のためのコンタクトパッドおよびコンタクトパッドの形成方法 Download PDF

Info

Publication number
JP5181261B2
JP5181261B2 JP2010511340A JP2010511340A JP5181261B2 JP 5181261 B2 JP5181261 B2 JP 5181261B2 JP 2010511340 A JP2010511340 A JP 2010511340A JP 2010511340 A JP2010511340 A JP 2010511340A JP 5181261 B2 JP5181261 B2 JP 5181261B2
Authority
JP
Japan
Prior art keywords
protrusions
contact pad
flat
protrusion
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010511340A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010529681A5 (https=
JP2010529681A (ja
Inventor
チャン，レイレイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of JP2010529681A publication Critical patent/JP2010529681A/ja
Publication of JP2010529681A5 publication Critical patent/JP2010529681A5/ja
Application granted granted Critical
Publication of JP5181261B2 publication Critical patent/JP5181261B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2010511340A 2007-06-05 2008-06-05 集積回路のためのコンタクトパッドおよびコンタクトパッドの形成方法 Active JP5181261B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/810,616 US7821132B2 (en) 2007-06-05 2007-06-05 Contact pad and method of forming a contact pad for an integrated circuit
US11/810,616 2007-06-05
PCT/US2008/065984 WO2008151301A1 (en) 2007-06-05 2008-06-05 A contact pad and method of forming a contact pad for an integrated circuit

Publications (3)

Publication Number Publication Date
JP2010529681A JP2010529681A (ja) 2010-08-26
JP2010529681A5 JP2010529681A5 (https=) 2011-11-24
JP5181261B2 true JP5181261B2 (ja) 2013-04-10

Family

ID=39671929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010511340A Active JP5181261B2 (ja) 2007-06-05 2008-06-05 集積回路のためのコンタクトパッドおよびコンタクトパッドの形成方法

Country Status (6)

Country Link
US (1) US7821132B2 (https=)
EP (1) EP2150975B1 (https=)
JP (1) JP5181261B2 (https=)
CN (1) CN101681900B (https=)
CA (1) CA2687424C (https=)
WO (1) WO2008151301A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110278054A1 (en) * 2010-05-14 2011-11-17 I-Tseng Lee Circuit board with notched conductor pads
US8766457B2 (en) 2010-12-01 2014-07-01 SK Hynix Inc. Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package
US9087830B2 (en) * 2012-03-22 2015-07-21 Nvidia Corporation System, method, and computer program product for affixing a post to a substrate pad
WO2014039546A1 (en) * 2012-09-05 2014-03-13 Research Triangle Institute, International Electronic devices utilizing contact pads with protrusions and methods for fabrication
WO2014093938A1 (en) * 2012-12-13 2014-06-19 California Institute Of Technology Fabrication of three-dimensional high surface area electrodes
US10376146B2 (en) 2013-02-06 2019-08-13 California Institute Of Technology Miniaturized implantable electrochemical sensor devices
US9536850B2 (en) * 2013-03-08 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
US10820844B2 (en) 2015-07-23 2020-11-03 California Institute Of Technology Canary on a chip: embedded sensors with bio-chemical interfaces
DE102016115848B4 (de) * 2016-08-25 2024-02-01 Infineon Technologies Ag Halbleiterbauelemente und Verfahren zum Bilden eines Halbleiterbauelements
US20200006273A1 (en) * 2018-06-28 2020-01-02 Intel Corporation Microelectronic device interconnect structure
US12057429B1 (en) * 2021-06-23 2024-08-06 Hrl Laboratories, Llc Temporary bonding structures for die-to-die and wafer-to-wafer bonding

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
US6313541B1 (en) * 1999-06-08 2001-11-06 Winbond Electronics Corp. Bone-pad with pad edge strengthening structure
JP2001168125A (ja) * 1999-12-03 2001-06-22 Nec Corp 半導体装置
DE10252556B3 (de) * 2002-11-08 2004-05-19 Infineon Technologies Ag Elektronisches Bauteil mit Außenkontaktelementen und Verfahren zur Herstellung einer Mehrzahl dieses Bauteils
US6959856B2 (en) * 2003-01-10 2005-11-01 Samsung Electronics Co., Ltd. Solder bump structure and method for forming a solder bump
KR100541396B1 (ko) * 2003-10-22 2006-01-11 삼성전자주식회사 3차원 ｕｂｍ을 포함하는 솔더 범프 구조의 형성 방법
US7170187B2 (en) * 2004-08-31 2007-01-30 International Business Machines Corporation Low stress conductive polymer bump
US7394159B2 (en) * 2005-02-23 2008-07-01 Intel Corporation Delamination reduction between vias and conductive pads

Also Published As

Publication number Publication date
US20080303152A1 (en) 2008-12-11
CA2687424C (en) 2013-09-24
WO2008151301A1 (en) 2008-12-11
CN101681900A (zh) 2010-03-24
CN101681900B (zh) 2011-12-07
US7821132B2 (en) 2010-10-26
EP2150975B1 (en) 2016-10-26
CA2687424A1 (en) 2008-12-11
EP2150975A1 (en) 2010-02-10
JP2010529681A (ja) 2010-08-26

Similar Documents

Publication Publication Date Title
JP5181261B2 (ja) 集積回路のためのコンタクトパッドおよびコンタクトパッドの形成方法
CN101236946B (zh) 布线板和半导体器件
KR101479512B1 (ko) 반도체 패키지의 제조방법
US12494414B2 (en) Semiconductor device with through-mold via
TWI466265B (zh) 積層型封裝體及其製造方法
KR20070073187A (ko) 다양한 크기의 볼 패드를 갖는 배선기판과, 그를 갖는반도체 패키지 및 그를 이용한 적층 패키지
JP4477966B2 (ja) 半導体装置の製造方法
JP2011142185A (ja) 半導体装置
US7790504B2 (en) Integrated circuit package system
US20130334684A1 (en) Substrate structure and package structure
CN101364578A (zh) 半导体器件和该半导体器件的制造方法
CN103620776A (zh) 半导体装置
US9368467B2 (en) Substrate structure and semiconductor package using the same
JP3824545B2 (ja) 配線基板、それを用いた半導体装置、それらの製造方法
US8283779B2 (en) Peel-resistant semiconductor device with improved connector density, and method of manufacturing the same
JP5543071B2 (ja) 半導体装置およびこれを有する半導体モジュール
KR100772103B1 (ko) 적층형 패키지 및 그 제조 방법
JP3848333B2 (ja) 半導体装置
JP4723312B2 (ja) 半導体チップおよび半導体装置
US20030057569A1 (en) Semiconductor device
KR101133126B1 (ko) 반도체 패키지 및 그 제조 방법
JP2008060159A (ja) 半導体装置およびその製造方法
JP2007165758A (ja) 半導体装置およびその製造方法
JP2004273552A (ja) 実装基板、及び電子部品と実装基板との組み合わせ
KR20080062565A (ko) 플립 칩 패키지

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110930

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111128

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111206

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120306

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121218

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121225

R150 Certificate of patent or registration of utility model

Ref document number: 5181261

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160125

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250