JP5122130B2 - 格子整合されなかった基板上に応力緩和層構造を形成する方法 - Google Patents

格子整合されなかった基板上に応力緩和層構造を形成する方法 Download PDF

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JP5122130B2
JP5122130B2 JP2006504230A JP2006504230A JP5122130B2 JP 5122130 B2 JP5122130 B2 JP 5122130B2 JP 2006504230 A JP2006504230 A JP 2006504230A JP 2006504230 A JP2006504230 A JP 2006504230A JP 5122130 B2 JP5122130 B2 JP 5122130B2
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layer
substrate
layer structure
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thickness
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マントル・ジークフリート
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フォルシュングスツェントルム・ユーリッヒ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツング
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3211—Silicon, silicon germanium or germanium
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Composite Materials (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Recrystallisation Techniques (AREA)
  • Light Receiving Elements (AREA)
JP2006504230A 2003-03-10 2004-02-06 格子整合されなかった基板上に応力緩和層構造を形成する方法 Expired - Lifetime JP5122130B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10310740A DE10310740A1 (de) 2003-03-10 2003-03-10 Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen
DE10310740.1 2003-03-10
PCT/DE2004/000200 WO2004082001A1 (de) 2003-03-10 2004-02-06 Verfahren zur herstellung einer spannungsrelaxierten schichtstruktur auf einem nicht gitterangepassten substrat sowie verwendung eines solchen schichtsystems in elektronischen und/oder optoelektronischen bauelementen

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JP2006522469A JP2006522469A (ja) 2006-09-28
JP2006522469A5 JP2006522469A5 (https=) 2011-10-13
JP5122130B2 true JP5122130B2 (ja) 2013-01-16

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US (1) US7442657B2 (https=)
EP (1) EP1604390B9 (https=)
JP (1) JP5122130B2 (https=)
AT (1) ATE464651T1 (https=)
DE (2) DE10310740A1 (https=)
WO (1) WO2004082001A1 (https=)

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Publication number Publication date
WO2004082001A1 (de) 2004-09-23
EP1604390A1 (de) 2005-12-14
EP1604390B9 (de) 2010-09-15
EP1604390B1 (de) 2010-04-14
DE502004011040D1 (de) 2010-05-27
JP2006522469A (ja) 2006-09-28
ATE464651T1 (de) 2010-04-15
US20060166475A1 (en) 2006-07-27
DE10310740A1 (de) 2004-09-30
US7442657B2 (en) 2008-10-28

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