JP5100012B2 - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
- Publication number
- JP5100012B2 JP5100012B2 JP2006013539A JP2006013539A JP5100012B2 JP 5100012 B2 JP5100012 B2 JP 5100012B2 JP 2006013539 A JP2006013539 A JP 2006013539A JP 2006013539 A JP2006013539 A JP 2006013539A JP 5100012 B2 JP5100012 B2 JP 5100012B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- groove
- layer
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Details Of Aerials (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006013539A JP5100012B2 (ja) | 2005-01-28 | 2006-01-23 | 半導体装置及びその作製方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005022191 | 2005-01-28 | ||
| JP2005022191 | 2005-01-28 | ||
| JP2006013539A JP5100012B2 (ja) | 2005-01-28 | 2006-01-23 | 半導体装置及びその作製方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006237581A JP2006237581A (ja) | 2006-09-07 |
| JP2006237581A5 JP2006237581A5 (enExample) | 2009-01-22 |
| JP5100012B2 true JP5100012B2 (ja) | 2012-12-19 |
Family
ID=37044835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006013539A Expired - Fee Related JP5100012B2 (ja) | 2005-01-28 | 2006-01-23 | 半導体装置及びその作製方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5100012B2 (enExample) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080018052A (ko) * | 2006-08-23 | 2008-02-27 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그 제조방법 |
| US8048777B2 (en) | 2006-09-29 | 2011-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| EP1962408B1 (en) * | 2006-11-16 | 2015-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Radio field intensity measurement device, and radio field intensity detector and game console using the same |
| CN102067281B (zh) * | 2008-04-25 | 2013-06-12 | 株式会社半导体能源研究所 | 半导体器件及其制造方法 |
| JP2010016240A (ja) * | 2008-07-04 | 2010-01-21 | Panasonic Corp | インダクタとその製造方法 |
| JP5407423B2 (ja) * | 2009-02-27 | 2014-02-05 | 大日本印刷株式会社 | 電子装置及び電子デバイス |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01272135A (ja) * | 1988-04-25 | 1989-10-31 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| JPH04343228A (ja) * | 1991-05-21 | 1992-11-30 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
| JPH05175198A (ja) * | 1991-12-25 | 1993-07-13 | Kawasaki Steel Corp | 半導体装置 |
| JP4332243B2 (ja) * | 1998-10-28 | 2009-09-16 | Tdk株式会社 | 薄膜コイル部品 |
| JP2003243631A (ja) * | 2002-02-18 | 2003-08-29 | Mitsubishi Electric Corp | 薄膜磁性体記憶装置ならびにそれを用いた無線チップ、流通管理システムおよび製造工程管理システム |
| JP4393859B2 (ja) * | 2002-12-27 | 2010-01-06 | 株式会社半導体エネルギー研究所 | 記録媒体の作製方法 |
| JP4323813B2 (ja) * | 2003-01-14 | 2009-09-02 | キヤノン株式会社 | 基板の製造方法 |
| JP4566578B2 (ja) * | 2003-02-24 | 2010-10-20 | 株式会社半導体エネルギー研究所 | 薄膜集積回路の作製方法 |
| JP2004355337A (ja) * | 2003-05-29 | 2004-12-16 | Toppan Forms Co Ltd | Rf−idメディア及びその製造方法、並びに情報書込/読出装置 |
| KR100598113B1 (ko) * | 2005-01-03 | 2006-07-07 | 삼성전자주식회사 | 인덕터 및 인덕터 형성 방법 |
-
2006
- 2006-01-23 JP JP2006013539A patent/JP5100012B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006237581A (ja) | 2006-09-07 |
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