JP5080174B2 - 半導体記憶装置の遅延ロックループ回路 - Google Patents

半導体記憶装置の遅延ロックループ回路 Download PDF

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Publication number
JP5080174B2
JP5080174B2 JP2007224001A JP2007224001A JP5080174B2 JP 5080174 B2 JP5080174 B2 JP 5080174B2 JP 2007224001 A JP2007224001 A JP 2007224001A JP 2007224001 A JP2007224001 A JP 2007224001A JP 5080174 B2 JP5080174 B2 JP 5080174B2
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Japan
Prior art keywords
pulse width
output
delay
unit
memory device
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Expired - Fee Related
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JP2007224001A
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Japanese (ja)
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JP2008154210A5 (enExample
JP2008154210A (ja
Inventor
錫 輔 沈
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SK Hynix Inc
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SK Hynix Inc
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2007224001A 2006-12-18 2007-08-30 半導体記憶装置の遅延ロックループ回路 Expired - Fee Related JP5080174B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2006-0129582 2006-12-18
KR1020060129582A KR100857429B1 (ko) 2006-12-18 2006-12-18 반도체 메모리 장치의 지연 고정 루프 회로

Publications (3)

Publication Number Publication Date
JP2008154210A JP2008154210A (ja) 2008-07-03
JP2008154210A5 JP2008154210A5 (enExample) 2010-09-30
JP5080174B2 true JP5080174B2 (ja) 2012-11-21

Family

ID=39526387

Family Applications (1)

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JP2007224001A Expired - Fee Related JP5080174B2 (ja) 2006-12-18 2007-08-30 半導体記憶装置の遅延ロックループ回路

Country Status (3)

Country Link
US (1) US7548101B2 (enExample)
JP (1) JP5080174B2 (enExample)
KR (1) KR100857429B1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101374336B1 (ko) * 2007-10-11 2014-03-17 삼성전자주식회사 메모리 시스템 및 이 시스템을 위한 반도체 메모리 장치와제어부
KR100894486B1 (ko) * 2007-11-02 2009-04-22 주식회사 하이닉스반도체 디지털 필터, 클록 데이터 복구 회로 및 그 동작방법, 반도체 메모리 장치 및 그의 동작방법
KR100956771B1 (ko) * 2007-12-11 2010-05-12 주식회사 하이닉스반도체 디엘엘 클럭 생성 회로
KR20090074412A (ko) * 2008-01-02 2009-07-07 삼성전자주식회사 분주회로 및 이를 이용한 위상 동기 루프
US7642827B2 (en) * 2008-05-28 2010-01-05 Micron Technology, Inc. Apparatus and method for multi-phase clock generation
US7719334B2 (en) * 2008-05-28 2010-05-18 Micron Technology, Inc. Apparatus and method for multi-phase clock generation
KR101062741B1 (ko) * 2009-01-06 2011-09-06 주식회사 하이닉스반도체 Ｄｌｌ 회로 및 그 제어 방법
KR101027759B1 (ko) 2009-12-22 2011-04-07 연세대학교 산학협력단 지연 동기 루프 및 그것의 듀티 사이클 보정 회로
US8471617B2 (en) 2010-06-17 2013-06-25 Hynix Semiconductor Inc. Duty cycle correction in a delay-locked loop
KR20120012119A (ko) * 2010-07-30 2012-02-09 주식회사 하이닉스반도체 레이턴시 제어 회로 및 그의 동작 방법
US8428204B2 (en) * 2010-08-20 2013-04-23 Raytheon Company Recovering distorted digital data
US8643418B2 (en) 2011-06-02 2014-02-04 Micron Technology, Inc. Apparatus and methods for altering the timing of a clock signal
US8786338B2 (en) * 2011-11-14 2014-07-22 Texas Instruments Incorporated Delay locked loop
KR102467451B1 (ko) * 2016-06-17 2022-11-17 에스케이하이닉스 주식회사 반도체 장치 및 반도체 시스템
CN109900971B (zh) * 2017-12-11 2023-01-24 长鑫存储技术有限公司 脉冲信号的处理方法、装置以及半导体存储器
KR102880562B1 (ko) * 2021-09-27 2025-11-05 에스케이하이닉스 주식회사 듀티보정회로를 포함하는 듀티보정장치 및 이를 포함하는 반도체 장치

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0693216B2 (ja) * 1987-04-27 1994-11-16 株式会社日立製作所 情報処理装置
US5133064A (en) * 1987-04-27 1992-07-21 Hitachi, Ltd. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
JPH05100763A (ja) * 1991-10-04 1993-04-23 Hitachi Ltd クロツク制御回路
JPH1069769A (ja) * 1996-08-29 1998-03-10 Fujitsu Ltd 半導体集積回路
KR100224718B1 (ko) * 1996-10-30 1999-10-15 윤종용 동기식 메모리장치의 내부 클락 발생기
KR100502675B1 (ko) * 2001-12-12 2005-07-22 주식회사 하이닉스반도체 레지스터 제어형 지연고정루프회로
KR100527399B1 (ko) * 2002-05-10 2005-11-15 주식회사 하이닉스반도체 반도체메모리장치의 디엘엘구동회로
KR100486268B1 (ko) * 2002-10-05 2005-05-03 삼성전자주식회사 내부에서 자체적으로 듀티싸이클 보정을 수행하는지연동기루프 회로 및 이의 듀티싸이클 보정방법
US6798248B2 (en) * 2002-12-20 2004-09-28 Intel Corporation Non-overlapping clock generation
JP2004273660A (ja) * 2003-03-07 2004-09-30 Renesas Technology Corp 半導体集積回路
KR100525096B1 (ko) * 2003-04-23 2005-11-01 주식회사 하이닉스반도체 Ｄｌｌ 회로
KR100515074B1 (ko) * 2003-04-29 2005-09-16 주식회사 하이닉스반도체 Ｄｌｌ 회로
KR100596433B1 (ko) * 2003-12-29 2006-07-05 주식회사 하이닉스반도체 반도체 기억 장치에서의 지연 고정 루프 및 그의 록킹 방법
KR100605588B1 (ko) 2004-03-05 2006-07-28 주식회사 하이닉스반도체 반도체 기억 소자에서의 지연 고정 루프 및 그의 클럭록킹 방법
KR100596781B1 (ko) * 2004-04-28 2006-07-04 주식회사 하이닉스반도체 온 다이 터미네이션의 종단 전압 조절 장치
KR100696957B1 (ko) * 2005-03-31 2007-03-20 주식회사 하이닉스반도체 클럭 듀티 조정 회로, 이를 이용한 지연 고정 루프 회로 및그 방법
KR100709475B1 (ko) * 2005-05-30 2007-04-18 주식회사 하이닉스반도체 Ｄｌｌ 회로의 듀티 사이클 보정회로

Also Published As

Publication number Publication date
US7548101B2 (en) 2009-06-16
JP2008154210A (ja) 2008-07-03
KR100857429B1 (ko) 2008-09-09
US20080143404A1 (en) 2008-06-19
KR20080056544A (ko) 2008-06-23

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