JP5066565B2 - 記憶素子及び記憶装置 - Google Patents
記憶素子及び記憶装置 Download PDFInfo
- Publication number
- JP5066565B2 JP5066565B2 JP2009506194A JP2009506194A JP5066565B2 JP 5066565 B2 JP5066565 B2 JP 5066565B2 JP 2009506194 A JP2009506194 A JP 2009506194A JP 2009506194 A JP2009506194 A JP 2009506194A JP 5066565 B2 JP5066565 B2 JP 5066565B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- electrode
- voltage
- sin
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/32—Material having simple binary metal oxide structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/33—Material including silicon
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/34—Material includes an oxide or a nitride
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
Description
2 電流抑制素子
3 記憶素子
3a 記憶素子(選択素子)
4 ビット線デコーダ
5 読み出し回路
6,7 ワード線デコーダ
11 立体交差部
20 記憶素子アレイ
21 記憶装置
31 第1の電極
32 第2の電極
33 電流抑制層
WL0〜WL3 ワード線
BL0〜BL3 ビット線
Vw 書き込み電圧
Vr 読み込み電圧
A,B,C 範囲
Claims (2)
- 極性が正又は負の電気パルスの印加によりその電気抵抗値が変化しかつ該変化した後の電気抵抗値を維持する抵抗変化素子と、
前記抵抗変化素子に前記電気パルスの印加時に流れる電流を抑制する電流抑制素子と、
を備え、前記抵抗変化素子と前記電流抑制素子とが直列に接続された記憶素子であって、
前記電流抑制素子は、第1の電極と、第2の電極と、前記第1の電極と前記第2の電極との間に配設された電流抑制層と、を備え、
前記電流抑制層が、SiNx(0<x≦0.85)により構成されており、
前記第1の電極及び前記第2の電極の少なくとも一方が、窒化タンタルを含んでいる、記憶素子。 - 極性が正又は負の電気パルスの印加によりその電気抵抗値が変化しかつ該変化した後の電気抵抗値を維持する抵抗変化素子と該抵抗変化素子に前記電気パルスの印加時に流れる電流を抑制する電流抑制素子とを備え、該電流抑制素子は第1の電極と第2の電極と該第1の電極と該第2の電極との間に配設された電流抑制層とを備え、該電流抑制層がSiNx(0<x≦0.85)により構成され、前記電流抑制層の膜厚が20nm以下であり、前記第1の電極及び前記第2の電極の少なくとも一方が、窒化タンタルを含んでいる、複数の記憶素子と、
複数のビット線と、
前記複数のビット線に各々立体交差する複数のワード線と、を備え、
前記複数の記憶素子は前記抵抗変化素子と前記電流抑制素子とが直列に接続されて構成されており、
前記複数の記憶素子が、前記ビット線と前記ワード線とが立体交差する各々の部分に配設され、該各々の部分において、前記直列回路の一端がその対応する前記ビット線に、前記直列回路の他端がその対応する前記ワード線に、各々接続されている、記憶装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009506194A JP5066565B2 (ja) | 2007-03-22 | 2007-11-30 | 記憶素子及び記憶装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007074513 | 2007-03-22 | ||
JP2007074513 | 2007-03-22 | ||
JP2009506194A JP5066565B2 (ja) | 2007-03-22 | 2007-11-30 | 記憶素子及び記憶装置 |
PCT/JP2007/073242 WO2008117494A1 (ja) | 2007-03-22 | 2007-11-30 | 記憶素子及び記憶装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012178318A Division JP5524296B2 (ja) | 2007-03-22 | 2012-08-10 | 記憶素子及び記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2008117494A1 JPWO2008117494A1 (ja) | 2010-07-15 |
JP5066565B2 true JP5066565B2 (ja) | 2012-11-07 |
Family
ID=39788236
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009506194A Active JP5066565B2 (ja) | 2007-03-22 | 2007-11-30 | 記憶素子及び記憶装置 |
JP2012178318A Active JP5524296B2 (ja) | 2007-03-22 | 2012-08-10 | 記憶素子及び記憶装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012178318A Active JP5524296B2 (ja) | 2007-03-22 | 2012-08-10 | 記憶素子及び記憶装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20100061142A1 (ja) |
EP (1) | EP2128901A4 (ja) |
JP (2) | JP5066565B2 (ja) |
KR (1) | KR101151594B1 (ja) |
CN (1) | CN101636841B (ja) |
WO (1) | WO2008117494A1 (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5050813B2 (ja) * | 2007-11-29 | 2012-10-17 | ソニー株式会社 | メモリセル |
CN101816070A (zh) | 2008-07-11 | 2010-08-25 | 松下电器产业株式会社 | 电流抑制元件、存储元件及它们的制造方法 |
US8355274B2 (en) * | 2008-09-19 | 2013-01-15 | Panasonic Corporation | Current steering element, storage element, storage device, and method for manufacturing current steering element |
JP4531863B2 (ja) | 2008-11-19 | 2010-08-25 | パナソニック株式会社 | 不揮発性記憶素子および不揮発性記憶装置 |
WO2011007538A1 (ja) * | 2009-07-13 | 2011-01-20 | パナソニック株式会社 | 抵抗変化型素子および抵抗変化型記憶装置 |
JP4703789B2 (ja) | 2009-07-28 | 2011-06-15 | パナソニック株式会社 | 抵抗変化型不揮発性記憶装置及びその書き込み方法 |
JP5406782B2 (ja) * | 2009-09-25 | 2014-02-05 | シャープ株式会社 | 不揮発性半導体記憶装置 |
JP4892650B2 (ja) * | 2010-03-18 | 2012-03-07 | パナソニック株式会社 | 電流制御素子、記憶素子、記憶装置および電流制御素子の製造方法 |
US8766231B2 (en) | 2011-03-07 | 2014-07-01 | Hewlett-Packard Development Company, L.P. | Nanoscale electronic device with barrier layers |
US9196753B2 (en) * | 2011-04-19 | 2015-11-24 | Micron Technology, Inc. | Select devices including a semiconductive stack having a semiconductive material |
JP5630742B2 (ja) * | 2011-12-05 | 2014-11-26 | 株式会社東芝 | 半導体記憶装置 |
US8563366B2 (en) | 2012-02-28 | 2013-10-22 | Intermolecular Inc. | Memory device having an integrated two-terminal current limiting resistor |
CN105144383B (zh) * | 2013-03-21 | 2019-11-19 | 汉阳大学校产学协力团 | 具有双向开关特性的双端子开关元件和电阻存储交叉点阵列 |
US8981327B1 (en) | 2013-12-23 | 2015-03-17 | Intermolecular, Inc. | Carbon-doped silicon based selector element |
US8975610B1 (en) | 2013-12-23 | 2015-03-10 | Intermolecular, Inc. | Silicon based selector element |
US9391119B2 (en) * | 2014-06-20 | 2016-07-12 | GlobalFoundries, Inc. | Non-volatile random access memory devices with shared transistor configuration and methods of forming the same |
JP6273184B2 (ja) * | 2014-09-03 | 2018-01-31 | 東芝メモリ株式会社 | 抵抗変化型記憶装置及びその製造方法 |
US9735360B2 (en) | 2015-12-22 | 2017-08-15 | Arm Ltd. | Access devices to correlated electron switch |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61174589A (ja) * | 1985-01-29 | 1986-08-06 | セイコーインスツルメンツ株式会社 | 液晶表示装置の製造方法 |
JPH04253024A (ja) * | 1991-01-30 | 1992-09-08 | Seiko Instr Inc | 電気光学装置 |
US6753561B1 (en) * | 2002-08-02 | 2004-06-22 | Unity Semiconductor Corporation | Cross point memory array using multiple thin films |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5155565A (en) * | 1988-02-05 | 1992-10-13 | Minnesota Mining And Manufacturing Company | Method for manufacturing an amorphous silicon thin film solar cell and Schottky diode on a common substrate |
JP2765967B2 (ja) * | 1989-07-26 | 1998-06-18 | 沖電気工業株式会社 | 半導体素子 |
JP2934677B2 (ja) * | 1990-02-01 | 1999-08-16 | セイコーインスツルメンツ株式会社 | 非線形抵抗素子の製造方法 |
JPH03283469A (ja) * | 1990-03-30 | 1991-12-13 | Toshiba Corp | 液晶表示装置 |
GB9113795D0 (en) * | 1991-06-26 | 1991-08-14 | Philips Electronic Associated | Thin-film rom devices and their manufacture |
JP4225081B2 (ja) * | 2002-04-09 | 2009-02-18 | 株式会社村田製作所 | 電子部品の製造方法、電子部品及び弾性表面波フィルタ |
US6917539B2 (en) * | 2002-08-02 | 2005-07-12 | Unity Semiconductor Corporation | High-density NVRAM |
WO2004032196A2 (en) * | 2002-10-03 | 2004-04-15 | Pan Jit Americas, Inc. | Method of fabricating semiconductor by nitrogen doping of silicon film |
JP2004319587A (ja) * | 2003-04-11 | 2004-11-11 | Sharp Corp | メモリセル、メモリ装置及びメモリセル製造方法 |
US6927074B2 (en) * | 2003-05-21 | 2005-08-09 | Sharp Laboratories Of America, Inc. | Asymmetric memory cell |
JP2005136115A (ja) * | 2003-10-30 | 2005-05-26 | Tdk Corp | 電子デバイス及びその製造方法 |
US20060063025A1 (en) * | 2004-04-07 | 2006-03-23 | Jing-Yi Huang | Method and system for making thin metal films |
EP1770778B1 (en) * | 2004-07-22 | 2012-03-14 | Nippon Telegraph And Telephone Corporation | Apparatus for obtaining double stable resistance values, method for manufacturing the same, metal oxide thin film and method for manufacturing the same |
US7646630B2 (en) * | 2004-11-08 | 2010-01-12 | Ovonyx, Inc. | Programmable matrix array with chalcogenide material |
JP2006203098A (ja) * | 2005-01-24 | 2006-08-03 | Sharp Corp | 不揮発性半導体記憶装置 |
US20060219546A1 (en) * | 2005-03-31 | 2006-10-05 | Chia-Hong Jan | Concentration-graded alloy sputtering target |
US7812404B2 (en) * | 2005-05-09 | 2010-10-12 | Sandisk 3D Llc | Nonvolatile memory cell comprising a diode and a resistance-switching material |
US20060250836A1 (en) * | 2005-05-09 | 2006-11-09 | Matrix Semiconductor, Inc. | Rewriteable memory cell comprising a diode and a resistance-switching material |
US7446010B2 (en) * | 2005-07-18 | 2008-11-04 | Sharp Laboratories Of America, Inc. | Metal/semiconductor/metal (MSM) back-to-back Schottky diode |
JP3889023B2 (ja) * | 2005-08-05 | 2007-03-07 | シャープ株式会社 | 可変抵抗素子とその製造方法並びにそれを備えた記憶装置 |
JP4167298B2 (ja) * | 2006-11-20 | 2008-10-15 | 松下電器産業株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
JP4137994B2 (ja) * | 2006-11-20 | 2008-08-20 | 松下電器産業株式会社 | 不揮発性記憶素子、不揮発性記憶素子アレイおよびその製造方法 |
US7382647B1 (en) * | 2007-02-27 | 2008-06-03 | International Business Machines Corporation | Rectifying element for a crosspoint based memory array architecture |
WO2008149493A1 (ja) * | 2007-06-01 | 2008-12-11 | Panasonic Corporation | 抵抗変化型記憶装置 |
-
2007
- 2007-11-30 KR KR1020097021953A patent/KR101151594B1/ko active IP Right Grant
- 2007-11-30 EP EP07832907A patent/EP2128901A4/en not_active Withdrawn
- 2007-11-30 WO PCT/JP2007/073242 patent/WO2008117494A1/ja active Search and Examination
- 2007-11-30 CN CN2007800522993A patent/CN101636841B/zh active Active
- 2007-11-30 US US12/532,552 patent/US20100061142A1/en not_active Abandoned
- 2007-11-30 JP JP2009506194A patent/JP5066565B2/ja active Active
-
2012
- 2012-08-10 JP JP2012178318A patent/JP5524296B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61174589A (ja) * | 1985-01-29 | 1986-08-06 | セイコーインスツルメンツ株式会社 | 液晶表示装置の製造方法 |
JPH04253024A (ja) * | 1991-01-30 | 1992-09-08 | Seiko Instr Inc | 電気光学装置 |
US6753561B1 (en) * | 2002-08-02 | 2004-06-22 | Unity Semiconductor Corporation | Cross point memory array using multiple thin films |
Also Published As
Publication number | Publication date |
---|---|
EP2128901A1 (en) | 2009-12-02 |
JP5524296B2 (ja) | 2014-06-18 |
JPWO2008117494A1 (ja) | 2010-07-15 |
KR101151594B1 (ko) | 2012-05-31 |
CN101636841A (zh) | 2010-01-27 |
WO2008117494A1 (ja) | 2008-10-02 |
US20100061142A1 (en) | 2010-03-11 |
EP2128901A4 (en) | 2013-01-09 |
KR20100008781A (ko) | 2010-01-26 |
JP2012253377A (ja) | 2012-12-20 |
CN101636841B (zh) | 2011-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5524296B2 (ja) | 記憶素子及び記憶装置 | |
JP4536155B2 (ja) | 電流抑制素子、記憶素子、及びこれらの製造方法 | |
JP4733233B2 (ja) | 電流抑制素子の製造方法 | |
JP3889023B2 (ja) | 可変抵抗素子とその製造方法並びにそれを備えた記憶装置 | |
CN103238185B (zh) | 非易失性半导体存储装置及其写入方法 | |
JP5270809B2 (ja) | 不揮発性記憶素子、及び不揮発性記憶装置 | |
JP5128718B2 (ja) | 不揮発性記憶素子の駆動方法および不揮発性記憶装置 | |
JP4892650B2 (ja) | 電流制御素子、記憶素子、記憶装置および電流制御素子の製造方法 | |
CN102648522A (zh) | 非易失性存储元件及其制造方法、以及非易失性存储装置 | |
JP5380612B2 (ja) | 不揮発性記憶素子の駆動方法及び初期化方法、並びに不揮発性記憶装置 | |
JP5291269B2 (ja) | 不揮発性半導体記憶素子、不揮発性半導体記憶装置およびその製造方法 | |
JP2008065953A (ja) | 不揮発性半導体記憶装置及びその読み出し方法 | |
WO2013150791A1 (ja) | 迂回電流を抑制する双方向型電流素子を用いたクロスポイント型の抵抗変化型記憶装置の設計方法 | |
CN102947935B (zh) | 电阻变化元件的制造方法 | |
US20140284545A1 (en) | In-Situ Nitride Initiation Layer For RRAM Metal Oxide Switching Material | |
WO2010032468A1 (ja) | 記憶素子及び記憶装置 | |
JP2014175419A (ja) | 電流制御素子、不揮発性記憶素子、不揮発性記憶装置および電流制御素子の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120529 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120627 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120724 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120813 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5066565 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150817 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |