JP4536155B2 - 電流抑制素子、記憶素子、及びこれらの製造方法 - Google Patents
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- 239000013077 target material Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
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- 238000005259 measurement Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
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- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- -1 TaSi 2 Chemical class 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Chemical Vapour Deposition (AREA)
- Physical Vapour Deposition (AREA)
Description
2 電流抑制素子
3 記憶素子
3a 記憶素子(選択素子)
4 ビット線デコーダ
5 読み出し回路
6,7 ワード線デコーダ
11 立体交差部
20 記憶素子アレイ
21 記憶装置
31 第2の電極
32 第1の電極
33 電流抑制層
40 下部電極
41 抵抗変化薄膜
42 上部電極
43 密着メタル層
44 ビア配線
45 絶縁膜
WL0〜WL3 ワード線
BL0〜BL3 ビット線
Claims (9)
- 極性が正または負の電気パルスの印加時に流れる電流を抑制する電流抑制素子であって、
前記電流抑制素子は、第1の電極と、電流抑制層と、第2の電極と、を備え、
前記第1の電極と前記第2の電極との間に前記電流抑制層が配設されることによりMSMダイオードが構成され、
前記電流抑制層が、SiNx(0<x≦0.85)により構成され、前記第1の電極及び前記第2の電極の少なくとも一方がα−タングステンにより構成されている、電流抑制素子。 - 前記式中のxが0.3≦x≦0.6を満たすことを特徴とする、請求項1記載の電流抑制素子。
- 第1の電極を形成する工程と、前記第1の電極上にSiNx(0<x≦0.85)で構成された電流抑制層を形成する工程と、前記電流抑制層上に第2の電極を形成して前記第1の電極と前記電流抑制層と前記第2の電極によりMSMダイオードを構成する工程と、を含む、極性が正または負の電気パルスの印加時に流れる電流を抑制する電流抑制素子の製造方法であって、
前記第1の電極及び前記第2の電極の少なくとも一方をα−タングステンにより形成する工程を含み、
前記電流抑制層を形成する工程は、多結晶シリコンからなるターゲットを用い、窒素を含む雰囲気中においてDCスパッタリングする工程を含むことを特徴とする、電流抑制素子の製造方法。 - 極性が正又は負の電気パルスの印加によりその電気抵抗値が変化しかつ該変化した後の電気抵抗値を維持する抵抗変化素子と、前記抵抗変化素子に前記電気パルスの印加時に流れる電流を抑制する電流抑制素子と、を備える記憶素子であって、
前記電流抑制素子は、第1の電極と、第2の電極と、前記第1の電極と前記第2の電極との間に配設された電流抑制層と、を備えることによりMSMダイオードを構成し、
前記電流抑制層が、SiNx(0<x≦0.85)により構成され、前記第1の電極及び前記第2の電極の少なくとも一方がα−タングステンにより構成されている、記憶素子。 - 前記式中のxが0.3≦x≦0.6を満たすことを特徴とする、請求項4記載の記憶素子。
- 極性が正または負の電気パルスの印加によりその電気抵抗値が変化しかつ該変化した後の電気抵抗値を維持する抵抗変化素子を形成する工程と、
前記抵抗変化素子に前記電気パルスの印加時に流れる電流を抑制する電流抑制素子を形成する工程と、を含む記憶素子の製造方法であって、
前記電流抑制素子を形成する工程は、第1の電極を形成する工程と、前記第1の電極上にSiNx(0<x≦0.85)で構成された電流抑制層を形成する工程と、前記電流抑制層上に第2の電極を形成して前記第1の電極と前記電流抑制層と前記第2の電極によりMSMダイオードを構成する工程と、を含み、
前記第1の電極及び前記第2の電極の少なくとも一方をα−タングステンにより形成する工程を含み、
前記電流抑制層を形成する工程は、多結晶シリコンからなるターゲットを用い、窒素を含む雰囲気中においてDCスパッタリングする工程を含むことを特徴とする、記憶素子の製造方法。 - 前記式中のxが0.3≦x≦0.6を満たすことを特徴とする、請求項6に記載の記憶素子の製造方法。
- 極性が正又は負の電気パルスの印加によりその電気抵抗値が変化しかつ該変化した後の電気抵抗値を維持する抵抗変化素子と、該抵抗変化素子に前記電気パルスの印加時に流れる電流を抑制する電流抑制素子とを備え、該電流抑制素子は第1の電極と第2の電極と該第1の電極と該第2の電極との間に配設された電流抑制層とを備えることによりMSMダイオードを構成し、該電流抑制層がSiNx(0<x≦0.85)により構成され、前記第1の電極及び前記第2の電極の少なくとも一方がα−タングステンにより構成されている複数の記憶素子と、
複数のビット線と、
前記複数のビット線に各々立体交差する複数のワード線と、を備え、
前記複数の記憶素子は前記抵抗変化素子と前記電流抑制素子との直列回路を備え、
前記複数の記憶素子が、前記ビット線と前記ワード線とが立体交差する各々の部分に配設され、該各々の部分において、前記直列回路の一端がその対応する前記ビット線に、前記直列回路の他端がその対応する前記ワード線に、各々接続されている、記憶装置。 - 前記式中のxが0.3≦x≦0.6を満たすことを特徴とする、請求項8記載の記憶装置。
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PCT/JP2009/001988 WO2010004675A1 (ja) | 2008-07-11 | 2009-05-01 | 電流抑制素子、記憶素子、及びこれらの製造方法 |
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US8422268B2 (en) | 2013-04-16 |
CN101816070A (zh) | 2010-08-25 |
JPWO2010004675A1 (ja) | 2011-12-22 |
WO2010004675A1 (ja) | 2010-01-14 |
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