JP5005718B2 - 保護バーを有する半導体パッケージ構造 - Google Patents
保護バーを有する半導体パッケージ構造 Download PDFInfo
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- JP5005718B2 JP5005718B2 JP2009065626A JP2009065626A JP5005718B2 JP 5005718 B2 JP5005718 B2 JP 5005718B2 JP 2009065626 A JP2009065626 A JP 2009065626A JP 2009065626 A JP2009065626 A JP 2009065626A JP 5005718 B2 JP5005718 B2 JP 5005718B2
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- 239000004065 semiconductor Substances 0.000 title claims description 33
- 230000001681 protective effect Effects 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 239000012778 molding material Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 229920001187 thermosetting polymer Polymers 0.000 claims description 11
- 239000004634 thermosetting polymer Substances 0.000 claims description 11
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 2
- 244000144980 herd Species 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 239000000945 filler Substances 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 238000012360 testing method Methods 0.000 description 9
- RKUAZJIXKHPFRK-UHFFFAOYSA-N 1,3,5-trichloro-2-(2,4-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC=C1C1=C(Cl)C=C(Cl)C=C1Cl RKUAZJIXKHPFRK-UHFFFAOYSA-N 0.000 description 8
- 230000035882 stress Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000002156 mixing Methods 0.000 description 3
- 206010011469 Crying Diseases 0.000 description 2
- 230000009194 climbing Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims (7)
- 半導体パッケージ構造であって、
キャリア基板と、
前記キャリア基板の頂面に設けられるIC(集積回路)ダイと、
前記頂面と前記ICダイを被覆・封止する成形材料と、
前記キャリア基板の底面に設けられる複数のはんだボールと、
前記キャリア基板の前記底面に設けられる少なくとも1本の保護バーとを含み、
前記保護バーは熱硬化性ポリマーでつくられ、
前記熱硬化性ポリマーの材料は、日立化成工業株式会社のCEL−1802−HF19−GZ、CEL−1802−HF19−GB、CEL−1802−HF19−GC、CEL−1802−HF19−GF、CEL−1802−HF19−GJ、及びCEL−1802−HF19−HAからなる群れから選ばれる、半導体パッケージ構造。 - 前記成形材料と前記保護バーは同一の材料でつくられる、請求項1に記載の半導体パッケージ構造。
- 前記保護バーは前記キャリア基板の前記底面の周縁に設けられる、請求項1に記載の半導体パッケージ構造。
- メモリモジュール構造であって、
PCB(プリント回路基板)と、
前記PCBに設けられる複数のメモリチップパッケージと、
前記メモリチップパッケージの各々を覆い、かつ、放熱接着剤を介して前記メモリチップパッケージの各々と熱的に接触するヒートシンクリッドとを含み、
前記メモリチップパッケージの各々は、請求項1乃至3のいずれか一項に記載の半導体パッケージ構造を有する、メモリモジュール構造。 - 前記成形材料と前記保護バーは同一の材料でつくられる、請求項4に記載のメモリモジュール構造。
- 前記保護バーは前記キャリア基板の前記底面の周縁に設けられる、請求項4に記載のメモリモジュール構造。
- 前記はんだボールは前記PCBに設けられるそれぞれ対応するボンドパッドに電気的に接続される、請求項4に記載のメモリモジュール構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW98100097A TWI466242B (zh) | 2009-01-05 | 2009-01-05 | 具有護桿的半導體封裝體結構 |
TW098100097 | 2009-01-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010157672A JP2010157672A (ja) | 2010-07-15 |
JP5005718B2 true JP5005718B2 (ja) | 2012-08-22 |
Family
ID=42243702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009065626A Active JP5005718B2 (ja) | 2009-01-05 | 2009-03-18 | 保護バーを有する半導体パッケージ構造 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7923852B2 (ja) |
JP (1) | JP5005718B2 (ja) |
DE (1) | DE102009013782A1 (ja) |
TW (1) | TWI466242B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009116517A1 (ja) * | 2008-03-17 | 2009-09-24 | 日本電気株式会社 | 電子装置及びその製造方法 |
JP5505171B2 (ja) * | 2010-07-30 | 2014-05-28 | 富士通株式会社 | 回路基板ユニット、回路基板ユニットの製造方法、及び電子装置 |
US9209046B2 (en) * | 2013-10-02 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
KR20220070687A (ko) * | 2020-11-23 | 2022-05-31 | 삼성전자주식회사 | 캐리어 필름, 마더 기판 및 이들을 이용한 반도체 패키지 제조 방법 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05206320A (ja) * | 1992-01-27 | 1993-08-13 | Nec Corp | マルチチップモジュール |
TW344109B (en) * | 1994-02-10 | 1998-11-01 | Hitachi Ltd | Methods of making semiconductor devices |
US5889333A (en) * | 1994-08-09 | 1999-03-30 | Fujitsu Limited | Semiconductor device and method for manufacturing such |
JPH10163386A (ja) * | 1996-12-03 | 1998-06-19 | Toshiba Corp | 半導体装置、半導体パッケージおよび実装回路装置 |
JP2907168B2 (ja) * | 1996-12-20 | 1999-06-21 | 日本電気株式会社 | 半導体装置および半導体装置と基板の接合構造 |
JP2000114427A (ja) * | 1998-10-07 | 2000-04-21 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000223608A (ja) * | 1999-01-29 | 2000-08-11 | Nec Corp | 半導体パッケージ及びその製造方法 |
US6291899B1 (en) * | 1999-02-16 | 2001-09-18 | Micron Technology, Inc. | Method and apparatus for reducing BGA warpage caused by encapsulation |
KR20010090354A (ko) * | 1999-03-26 | 2001-10-18 | 가나이 쓰토무 | 반도체 모듈 및 그 실장 방법 |
JP2002083904A (ja) * | 2000-09-06 | 2002-03-22 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US6459144B1 (en) * | 2001-03-02 | 2002-10-01 | Siliconware Precision Industries Co., Ltd. | Flip chip semiconductor package |
US6486554B2 (en) * | 2001-03-30 | 2002-11-26 | International Business Machines Corporation | Molded body for PBGA and chip-scale packages |
US7215022B2 (en) * | 2001-06-21 | 2007-05-08 | Ati Technologies Inc. | Multi-die module |
JP2002208657A (ja) * | 2001-11-28 | 2002-07-26 | Fujitsu Ltd | 半導体装置及び半導体装置実装用基板 |
US6906425B2 (en) * | 2002-03-05 | 2005-06-14 | Resolution Performance Products Llc | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
US7323767B2 (en) * | 2002-04-25 | 2008-01-29 | Micron Technology, Inc. | Standoffs for centralizing internals in packaging process |
US6969914B2 (en) * | 2002-08-29 | 2005-11-29 | Micron Technology, Inc. | Electronic device package |
JP4390541B2 (ja) * | 2003-02-03 | 2009-12-24 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US7445141B2 (en) * | 2004-09-22 | 2008-11-04 | International Business Machines Corporation | Solder interconnection array with optimal mechanical integrity |
US20070013054A1 (en) * | 2005-07-12 | 2007-01-18 | Ruchert Brian D | Thermally conductive materials, solder preform constructions, assemblies and semiconductor packages |
-
2009
- 2009-01-05 TW TW98100097A patent/TWI466242B/zh active
- 2009-02-03 US US12/364,525 patent/US7923852B2/en active Active
- 2009-03-18 JP JP2009065626A patent/JP5005718B2/ja active Active
- 2009-03-18 DE DE200910013782 patent/DE102009013782A1/de not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
US20100171212A1 (en) | 2010-07-08 |
US7923852B2 (en) | 2011-04-12 |
TWI466242B (zh) | 2014-12-21 |
JP2010157672A (ja) | 2010-07-15 |
DE102009013782A1 (de) | 2010-07-15 |
TW201027678A (en) | 2010-07-16 |
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