A7 —_______H7 五、發明説明（1 ) 一 本發明所屬之技術領域 本發明係有關於-種可封裝在記憶基板或主機板等之 半導體裝置及其製造方法。 習知技藝及本發明欲解決之課題 習知之半導艘晶片，係以封裝之狀態作組裝。又，亦 有將多數之半導體晶片封裝在基板上，以構成多晶片模組 之場合。以如是所封裝之半導體晶片或封裝在模組基板之 半導艘晶片，乃以i或多數個作為單位進行良否檢查但 。若欲檢查之半導體晶片數較多之場合，成為所欲檢查之 單位的半導體晶片數較少之時，即，其檢查效率就隨之而 降低，是故，乃需求能提升檢查效率之方法。 ,本發明翁餘上述課題而·作者^以提供能提 升半導體晶片之良否檢查效率的半導體裝置及其製造方法 ’為目的。 欲解決課題之本發明裝置 經濟部中央標準局員工消費合作社印裝 欲解決上述之課題的本發明之装置，係於將多數之半 導趙晶片（以記憶艘晶片為宜）封裝在基板上，並以樹脂封 閉之狀態下，進行各半導體晶片之良否檢查之後，將所定 個數作為單位，切割半導體晶片而形成半導體裝置。因為 ，半導體晶片之良否檢查’係以基板作為單位而進行，是 故，其比將1或少數個之半導體晶片，以個別作檢查之場 合’能予提升檢查效率。 特別疋，將半導體晶片封裴於基板之一面上而介著 形成在其另-面上之端子，作各半導體晶片之良否檢查為 本紙張尺度適用中國mtm- ( CNS ) ( 210χ1^ΓΤ -4- 經濟部中央標準局貝工消費合作社印¾ A7 -----B7 五、發明説明（2 ) 佳。於此場合，係以1片基板整體視為〗個組件作處理因 之，能作所封裝之多數的半導體晶片之良否檢查，是故， 其比以個別所封裝之半導體晶體，或封裝多數個半導體晶 片之半導體練’作為單位而進行良否檢纟之場合，能予 減少於良否檢查上所化費之時間與精神。 本發明之實施態樣 以下，參照圖面針對適用本發明之一實施態樣的記憶 體模組，作具體性說明。第！圖係表示本實施態樣之記憶 體模組的製造工程。如在該圖⑷所示，作為半導體裝置 之記憶體模組10，係由從半導體晶圓所切割之記憶體用對 偶晶片（記憶體晶片）1、封裝記憶體用對偶晶片丨之基板2 、欲封閉經封裝記憶體用對偶晶片丨之基板2面的樹脂3, 所構成。 首先，如第1圖（a)及（b)所示，導入基板2，並將多數 之記憶體用對偶晶片1，而以縱橫各自之所定間隔，配置 且封裝於基板2上之一面上(第】工程)。各記憶體用對偶晶 片1的封裝方法方面，例如，採用COB (Chip 〇n B〇ard)封 裝。 第2圖係表示封裝記憶體用對偶晶片丨之前的基板2的 部份構造。該圖（a)係表示封裝記憶體用對偶晶片丨之面， 而該圖(b)係表示其相反面(背面）。又該圖⑷係表示從側 面所觀看之構造。如在該等圖所示，基板2在記憶體用對 偶晶片1所封裝之各所定領域，與記憶體用對偶晶片丨之間 ，有形成為進行電氣性連接所必要之基板用墊皮11，而該 本紙張尺度適用中國國家標準（CNS ) Λ4規搞（210X 297公17 - . ^^1 I»i ----- ti^i in I» nn nn i— ^^^1 (对.先閱#作而之注意麥項#填寫本頁) 經濟部中央標準局員工消費合作社印裝 A7 j__________H7 五、發明説明（3 ) ~ 基板用墊皮11介著通孔12，與背侧之BGA (Ball Grid八⑽力 用墊皮13作電氣性連接。 第3圖係表示於第2圖所示之基板2上，於第ι工程封 裝記憶體用對偶晶片i之狀態。第3圖⑷係表示記憶體用 對偶晶片1之封裝面的構造，而該圖（b)係表示從側面所觀 看之構造。各記憶體用對偶晶片丨，例如為，具有ΐ6Μχ4 位το之容量的DRAM，而在其表面，乃沿著長邊於其中央 形成一列之晶片用墊皮14。該晶片用墊皮14，乃使用形成 在基板2上之基板用墊皮n，與結合電線15作連接。對各 記憶體用對偶晶片1均使用如是之結合電線丨5作(：〇8封裝 〇 於上述之第1工程上，將記憶體用對偶晶片丨封裝於基 板2之後，如第1圖（c)所示，在封裝記憶體用對偶晶片】之 基板2的面上灌入樹脂3，並以所定厚度之樹脂3封閉各記 憶體用對偶晶片1(第2工程）。 於第2工程上，由於依樹脂3封閉各記憶體用對偶晶片 1，因而防止連接在記憶體用對偶晶片丨之結合電線15的斷 線或短路。又，將樹脂3作為所定厚度，因而抑制所製造 之記憶體模組10的高度之不均（偏差）。 其次，以如是依樹脂3作封閉之狀態下，進行各記憶 鱧用對偶晶片1之良否檢查（第3工程）。例如，在形成於基 板2之背面的BGA用墊皮13，押壓檢查用探針而作電性接 觸，即，可實施各種之機能試驗。由於將基板2之整體作 為單位，而進行記憶體用對偶晶片1之良否檢查，即，由 本紙张尺度it用+國國家料（CNS ) Λ術# ( 2敝297公势) '~~ ---- (^先閱讀背而_之注意^項#^-寫本頁) 束· 訂 -6- Λ7 Β7 五、發明説明（4 ) 於將封裝在基板2之多數的記憶體用對偶晶片丨，以丨次進 行其良否檢查，以圖提升其檢查效率。 其次’以第3工程上之良否檢查的結果為依據，如在 第1圖（d)所示，將經予判定為良品之記憶體用對偶晶片！ ，切割為1個（或為所定之多數個）而完成為記憶體模組丨〇( 第4工程）。 第4圖係表示封裝在基板2之記憶體用對偶晶片1的良 否檢查（第3工程）之結果，圖中，〇符號與χ符號，乃分 別表示經判定為良品與不良品之記憶體用對偶晶片1。其 將封裝在基板2之多數的記憶體用對偶晶片丨集中作檢查， 而可獲得表示其良否之矩陣狀之檢查結果。在第4工程， 就從所切割之記憶體模組1〇之中，取除不良品並僅予取出 良品。 如疋，將基板2整體作為單位而集中作封裝在基板2之 多數的記憶體用對偶晶片丨之良否檢查，是故，其比對切 割後之各個記憶體模組1〇進行良否檢查之場合，能予提升 檢查效率。 經濟部中央標準局貝工消費合作社印^ '未-- .-f (請先閲请1)··而.之注意Ψ-*項4填寫本頁) 又，S己憶體用對偶晶片雖可以丨個或多數個（2個或4個 )作為單位而切割，惟，儘量以較多之個數作為組體而切 割，即，儘量以每4個作切割，因之，能以良好效率製造 取4個為組之記憶體模組。 本發明並非限定於上述之實施態樣，而在本發明之要 旨的範圍内可作種種之變形實施。例如，在上述之實施態 樣’乃以電線結合進行封裝，但，以浮片晶片 而將記 本紙張尺度適用中國國家標準（CNS ) Λ4規;|Γ?Τ5^^97公& 經濟部中央標準局員工消費合作社印裝 Μ _____Η 7 五、發明説明（5 ) ~~ 憶體用對偶晶片1作封裝亦可以。第5圖係表示浮片晶片封 裝之場合的記憶體用對偶晶片丨，與基板2之連接狀態。如 在該圖所示’將形成在記憶體用對偶晶片1之封裝面的基 板用整皮’及形成在欲封裝記憶體用對偶晶片1之基板2面 的晶片用墊皮，相對向並依塊形連接端子2丨作連接，就可 作浮片晶片封裝。依據浮片晶片封裝’即，可作更高密度 封裝，因之，可使所製造之記憶體模組1〇之外形尺寸更予 小型化。又，由該等之DRAMa首之各種半導體晶片，由 於其動作速度之高速化，因此，其配線長度以愈短愈佳， 而採用浮片封裝，即，能予實現更短之配線長度。 又，在上述之實施態樣，由於在基板2上載置各記憶 體用對偶晶片1後，再從其上面作C0B封裝之故，在基板2 上會突出各記憶體用對偶晶片丨，或結合電線丨5，但就 將各記憶體用對偶晶片1收納在基板2内，使結合電線15等 不予露出在外部之CIB (Chip In Board)構造亦可以。第6圖 係表示具有CIB構造之記憶體用對偶晶片丨與基板2之截面 。如在該圊所示，在基板2形成凹部，而在其凹部之内部 封裝δ己憶體用對偶晶片1 ,並使基板用墊皮丨丨與晶片用墊 皮14，配置於大約為同一面上，因之，就能將封裝之時的 電線結合裝置之毛細作用的上下方向之移動減少，並可提 升作業效率。又，因為，在記憶體用對偶晶片丨之端部， 不會有結合電線15接觸，是故，於該部份之配線的短路現 象就可消除’並可使不良率降低。 又，在上述之實施態羡，雖僅予灌入樹脂3，以封 ------ I t^i ---' - - - n n - T I I _ _ _ n fC 、-*0 m 7 ("先閱讀背而"'注意事項再填寫本頁) -8- A7 _____H7 五、發明説明（6 ) 封裝在基板2之§己憶體用對偶晶片1的基板面，惟依射出成 型之轉移模型所作之樹脂封閉亦可以。第7圖係說明依轉 移模型作樹脂成型，該圖（a)係表示在基板2整體進行平坦 之樹脂成型之場合’而該圖（b)為該圖（a)之變形例，並在 沿著切割線設有溝槽之場合。依轉移模型作樹脂成型，由 於能縮短成型時間，因之，適用於大量生產。 又，在上述之實施態樣，其記憶體模組1〇之外部連接 端子方面’係使用BGA用墊皮13，惟，使用所謂之Lcc (Leadless Chip Carrier)方式之端子亦可以。 第8圖係表示使用LCC方式之外部連接端子之場合的 3己憶艘模組10之部份構造。如該圖所示，切割後之記憶體 模組10之侧面之中，在縱方向或橫方向之任—方向（或為 雙方亦可以）’形成凹部並如同覆蓋該凹部表面般，而作 金屬電鍍就可形成外部連接端子31» 經濟部中央橾準局貝工消費合作社印製 ---------- 私-- > j (誚先閱讀.f而之注意事項再填寫本頁) 第9圊係說明LCC方式之外部連接端子3丨的形成過程 。如在該圖（a)所示，於基板2a，欲切割所封裝之記憶體 用對偶晶片丨之切割線之中，沿在縱方向或橫方向之任一 方向（或雙方向）’形成通孔32。但是，將該基板2a直接使 用於3己憶體模組1〇之製造時，即，於上述之第2製造工程 上作樹脂封閉之時，因所灌入之樹脂3而使外部連接端子31 有發生阻塞（網目阻塞）之場合存在。由於此，如在該圖（b) 所示，乃沿著通孔32而予形成絕緣膠帶33等之保護部材， 以防止樹脂3流入通孔32 ^或者，事先於各通孔32予以灌 流薛錫等，使其不因樹脂之灌入而發生阻塞，亦可以。然 -9- A7 Η 7 經濟部中央標準局貝工消費合作社印裂 五、發明説明（ 後，將上述之通孔32於其中央予以切斷，就可形成為如第 8圓所示之外部連接端子3 1。 又’於上述之實施態樣所使用之基板2方面，使用可 母性基板或其他之各種基板均可以。又，在上述之實施態 樣，半導體晶片係使用記憶體晶片，並以欲製造半導體裝 置之記憶體模組之場合為例作其說明，但，記憶體晶片以 外之半導體晶片，亦能適用，例如，處理機晶片或將ASI c 等之各種晶片封裝於基板上之場合。又，從基板2所欲切 割之s己憶體用對偶晶片1，並非以每丨個作切割，乃以2個 以上之所疋個數作為单位而作切割，亦可以。 本發明之效果 如上述，依據本發明，係將封裝多數之半導體晶片的 基板整體作為單位，而進行半導體晶片之良否檢查之故， 其比1或少數個之半導體晶片以個別作檢查之場合，能予 提升檢查效率。 圖式之簡單說明 第1圖係表示本實態樣之記憶體模組的製造工程； 第2圖係表示封裳記憶體用對偶晶片之前的基板之部 份性構造； 第3圓係表示於第2圖所示之基板上封|記意體用對偶 晶片之狀態。 第4圖係表示封裝於基板之記憶體用對偶晶片的良否 檢查之結果； 第圖係表不於浮片晶片封裝之場合的記憶體用對偶 n - —^1 ili - - n I I I —— - I 口 : > (讀先閲..謂背而之注意事項再填寫本頁) ~ 10 ~ 五、發明説明（ Λ7 B7 晶片與基板之連接狀態；第ό圖係表示具有c丨B構造之記憶體用對偶 板之截面； 晶片與基 第7圖係表示依轉移模型作樹脂成型之概要說明； 第8圖係表示使用LCC方式之外部連接端子的場合 記憶體模組的部份性構造； 第9圖係說明使用LCC方式之外部連接端子之場合的 外部連接端子之形成過程。 之 (ΐί先閱讀背而之注-A:t項#填β本頁)A7 —_______ H7 V. Description of the invention (1) 1. Technical field to which the present invention pertains The present invention relates to a semiconductor device which can be packaged in a memory substrate or a motherboard, and a method for manufacturing the same. Known techniques and problems to be solved by the present invention The conventional semi-conductor wafers are assembled in a packaged state. There are also cases where a large number of semiconductor wafers are packaged on a substrate to constitute a multi-chip module. For the packaged semiconductor wafer or the semi-conductor wafer packaged in the module substrate, a good or bad inspection is performed with i or a plurality as the unit. If the number of semiconductor wafers to be inspected is large, and the number of semiconductor wafers to be the unit to be inspected is small, that is, the inspection efficiency is reduced accordingly. Therefore, it is necessary to improve the inspection efficiency. The subject of the present invention is to solve the above problems and the authors aim to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the efficiency of semiconductor wafers. The device of the invention for solving the problem The device of the invention of the employee's cooperative of the Central Standards Bureau of the Ministry of Economic Affairs printed the device of the invention for solving the above-mentioned problems, which is based on packaging most of the semiconductor chips (preferably memory chips) on a substrate. After the semiconductor wafers are inspected for goodness or failure with the resin sealed, the predetermined number is used as a unit to cut the semiconductor wafers to form a semiconductor device. Because "good or bad inspection of semiconductor wafers" is performed by using a substrate as a unit, it can improve inspection efficiency compared to the case where one or a few semiconductor wafers are individually inspected ". In particular, the semiconductor wafer is sealed on one side of the substrate and the terminals formed on the other side of the substrate are tested for the goodness of each semiconductor wafer. The paper standard is applicable to China mtm- (CNS) (210χ1 ^ ΓΤ -4 -Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics ¾ A7 ----- B7 V. The description of the invention (2) is good. In this case, a whole substrate is regarded as one component for processing. The good or bad inspection of the majority of the packaged semiconductor wafers is therefore less effective than the good or bad inspections performed by using individual packaged semiconductor crystals or semiconductor packages that package a large number of semiconductor wafers as a unit. The time and spirit of the above. The embodiment of the present invention is described below with reference to the drawings for a specific description of a memory module to which one of the embodiments of the present invention is applied. The first! The picture shows the embodiment of the present embodiment Manufacturing process of a memory module. As shown in the figure ⑷, the memory module 10 as a semiconductor device is a dual chip (memory chip) for a memory diced from a semiconductor wafer, and a package. The substrate 2 for the memory dual chip 丨 and the resin 3 for sealing the substrate 2 of the dual chip for the sealed memory 丨. First, as shown in Fig. 1 (a) and (b), the substrate 2 is introduced. , And the majority of the memory uses the dual chip 1 and is arranged and packaged on one surface of the substrate 2 at a predetermined interval in the vertical and horizontal directions (the first process). For each memory, the dual chip 1 is packaged, for example, COB (Chip 〇n B〇ard) package is used. Figure 2 shows a part of the structure of the substrate 2 before the dual chip for memory packaging. Figure (a) shows the face of the dual chip for memory packaging. The figure (b) shows the opposite side (back side). The figure shows the structure viewed from the side. As shown in these figures, the substrate 2 is fixed in the memory chip paired with the dual chip 1. In the field, there is a pad 11 for the substrate necessary for the electrical connection between the memory chip and the dual chip. The size of this paper applies the Chinese National Standard (CNS) Λ4 Regulation (210X 297 Public 17-. ^ ^ 1 I »i ----- ti ^ i in I» nn nn i— ^^^ 1 (Yes. First # 作 而 之 NO 麦麦 项 #Fill in this page) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 j__________H7 V. Description of the invention (3) ~ The pad 11 for the substrate passes through the through hole 12, and the BGA on the back side (Ball The Grid Eight Force Pads 13 are used for electrical connection. Figure 3 shows the state of the dual chip i in the memory packaged on the substrate 2 shown in Figure 2. Figure 3 shows the memory. The structure of the package surface of the dual-use dual chip 1 is shown in (b) of the figure, as viewed from the side. Each dual-chip dual-use memory is, for example, a DRAM with a capacity of ΐ6M × 4 bits το, , Is a row of wafer pads 14 formed in the center along the long side. This wafer pad 14 is connected to a bonding wire 15 using a substrate pad n formed on the substrate 2. For each memory dual chip 1, use the combined wires as described above. 5 is used for packaging: (0) package 0. After the dual chip for memory is packaged on the substrate 2 as shown in Figure 1 (c As shown in the figure, a resin 3 is poured into the surface of the substrate 2 for the memory dual chip], and each of the memory dual wafers 1 is sealed with the resin 3 of a predetermined thickness (second process). In the second process, Since each of the memory dual wafers 1 is closed by the resin 3, disconnection or short-circuiting of the bonding wire 15 connected to the memory dual wafers 丨 is prevented. Furthermore, the resin 3 is used as a predetermined thickness, thereby suppressing the manufactured memory mold. The unevenness (deviation) of the height of the group 10. Next, the goodness of each memory chip pairing wafer 1 is checked under the condition that the resin 3 is closed (third process). For example, it is formed on the back surface of the substrate 2. The BGA pad 13 is used for electrical contact by pressing the probe for inspection, that is, various functional tests can be performed. Since the entire substrate 2 is used as a unit, the goodness of the dual chip 1 for memory is inspected, that is, By this paper rule It uses + country materials (CNS) Λ 术 # (2 敝 297 public power) '~~ ---- (^ Read the back first__notes ^ Item # ^-Write this page) 本页 · -6- Λ7 Β7 V. Description of the invention (4) The duality wafers for the majority of the memory packaged on the substrate 2 are checked for good or bad times in order to improve the inspection efficiency. Secondly, the "good or bad check for the third project" Based on the results, as shown in Figure 1 (d), the memory chip dual chip that has been judged to be good! Is cut into 1 (or a predetermined majority) to complete the memory module 丨〇 (4th process). Figure 4 shows the results of the good or bad inspection (the 3rd process) of the dual chip 1 for the memory chip packaged on the substrate 2. The 〇 and χ symbols in the figure respectively indicate that they are judged to be good The dual chip 1 for memory with defective products. The majority of the dual chip DIMMs for memory packaged on the substrate 2 are collectively inspected, and a matrix-like inspection result indicating good or bad can be obtained. In the fourth project, from In the cut memory module 10, remove the defective products and only take out the good ones. If so, place the substrate 2 The body is used as a unit to concentrate the inspection of the goodness of the dual memory chips for the majority of the memory packaged on the substrate 2. Therefore, it can improve the inspection efficiency when comparing the goodness of each memory module 10 after cutting. Printed by Shellfish Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs ^ 'Not-.-f (please read 1 first) ... and note Ψ-* item 4 to fill out this page) Also, S has a dual chip for memory Although it can be cut by one or more (two or four) as a unit, try to cut as many groups as possible, that is, try to cut every four as much as possible. Efficient manufacturing takes 4 memory modules as a group. The present invention is not limited to the embodiments described above, but various modifications can be made within the scope of the gist of the present invention. For example, in the above-mentioned embodiment, the package is wire-bonded. However, the paper size of the notebook paper is applied to the Chinese National Standard (CNS) Λ4 regulation by floating chip; | Γ? Τ5 ^^ 97 公 & Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards _____ Η 7 V. Description of the Invention (5) ~~ Memories can also be packaged with dual chip 1. Fig. 5 is a diagram showing the connection state of the memory dual chip 丨 and the substrate 2 when the floating chip is packaged. As shown in the figure, "the entire substrate for the substrate formed on the packaging surface of the memory dual chip 1" and the substrate for the wafer formed on the two surfaces of the substrate 1 of the dual wafer 1 to be packaged are opposite to each other The block-shaped connection terminal 2 can be connected to form a floating chip package. According to the floating chip package, that is, a higher density package can be used, and therefore, the manufactured memory module 10 can be miniaturized in outer shape. In addition, since various semiconductor wafers such as DRAMa have a high operating speed, their wiring lengths should be as short as possible, and floating chip packages can be used to achieve shorter wiring lengths. Furthermore, in the above embodiment, since the memory dual wafers 1 are placed on the substrate 2 and then the COB package is mounted thereon, the memory dual wafers may be protruded on the substrate 2 or combined. Wires 5, but a CIB (Chip In Board) structure in which each memory dual chip 1 is housed in the substrate 2 so that the bonding wires 15 and the like are not exposed to the outside may be used. FIG. 6 is a cross-section of a dual wafer for memory having a CIB structure and a substrate 2. As shown in this figure, a recessed portion is formed in the substrate 2 and the delta wafer 1 for the hexahedron is packaged inside the recessed portion, and the substrate pad 丨 丨 and the wafer pad 14 are disposed on approximately the same surface. As a result, the vertical movement of the capillary action of the wire bonding device at the time of packaging can be reduced, and work efficiency can be improved. In addition, since there is no contact of the bonding wire 15 at the end of the memory dual chip, the short circuit phenomenon of the wiring at this portion can be eliminated 'and the defective rate can be reduced. In the above-mentioned embodiment, although only the resin 3 is injected to seal -------- I t ^ i --- '---nn-TII _ _ _ n fC,-* 0 m 7 (" Read the back first " 'Precautions and then fill out this page) -8- A7 _____H7 V. Description of the invention (6) § The substrate surface of the dual wafer 1 of the self-memory body packaged on the substrate 2 is subject to injection molding Resin closure made by the transfer model is also possible. Fig. 7 illustrates resin molding according to the transfer model. Fig. (A) shows a case where a flat resin is formed on the entire substrate 2 ', and Fig. (B) is a modified example of Fig. (A), and is shown along the line. Where grooves are provided along the cutting line. Resin molding according to the transfer model can shorten the molding time and is therefore suitable for mass production. In the above embodiment, the BGA pad 13 is used as the external connection terminal of the memory module 10; however, a so-called Lcc (Leadless Chip Carrier) type terminal may be used. Fig. 8 is a diagram showing a part of the structure of the 3 Jiyi module 10 when an external connection terminal of the LCC method is used. As shown in the figure, among the sides of the cut memory module 10, a recess is formed in any one of the vertical and horizontal directions (or both sides) to form a recess and cover the surface of the recess as a metal. External connection terminals can be formed by electroplating 31 »Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ---------- Private-&j; (诮 Read the f first, then fill out this note (Page 9) describes the formation process of the external connection terminal 3 of the LCC method. As shown in (a) of the figure, among the cutting lines of the substrate 2a, the memory chip to be packaged is to be cut in one of the vertical or horizontal directions (or both directions).孔 32。 Hole 32. However, when the substrate 2a is directly used in the manufacture of the 3D memory module 10, that is, when the resin is sealed in the second manufacturing process described above, the external connection terminal 31 is caused by the resin 3 being poured therein. There are occasions where blocking occurs (net blocking). Because of this, as shown in (b) of the figure, a protective member such as an insulating tape 33 is formed along the through-holes 32 to prevent the resin 3 from flowing into the through-holes 32 ^ Or, the perforation of the through-holes 32 is performed in advance. It is also possible to prevent tin from blocking due to resin infusion. Ran-9- A7 Η 7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (After the above-mentioned through-hole 32 is cut off in the center, it can be formed as an outer part shown in circle 8 Connection terminal 31. In addition, as for the substrate 2 used in the embodiment described above, a mother substrate or various other substrates may be used. Also, in the embodiment described above, the semiconductor wafer is a memory wafer, and A case where a memory module of a semiconductor device is to be manufactured is taken as an example for explanation. However, a semiconductor wafer other than a memory wafer can also be applied, for example, a processor wafer or various chips such as ASI c packaged on a substrate. Occasion. Moreover, the dual wafer 1 for the s-memory body to be cut from the substrate 2 is not cut with each of them, but is cut with two or more of the numbers as a unit. The present invention is also applicable. The effect is as described above. According to the present invention, the entire substrate of a large number of semiconductor wafers is taken as a unit, and the quality of the semiconductor wafer is checked. In the case of inspection, the inspection efficiency can be improved. Brief description of the drawing The first diagram shows the manufacturing process of the memory module in the actual state; the second diagram shows the part of the substrate before the dual chip used for sealing memory Partial structure; The third circle shows the state of sealing the dual chip for the memory on the substrate shown in Figure 2. The fourth figure shows the result of the quality check of the dual chip for the memory packaged on the substrate; The picture shows the memory pair n-— ^ 1 ili--n III ——-I port: > (Read first read: Precautions that are contradictory before filling this page ) ~ 10 ~ V. Description of the invention (Λ7 B7 The connection state between the chip and the substrate; Figure 6 shows the cross-section of a dual board for a memory with a c 丨 B structure; Figure 7 shows the wafer and the base. The outline of molding; Figure 8 shows the partial structure of the memory module when using the external connection terminal of the LCC method; Figure 9 shows the formation process of the external connection terminal when using the external connection terminal of the LCC method . (Ϊ́ί first read back The Note -A: t Page Item # fill β)
P 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家榡準（CNS ) Λ4規輅（210x297公费） -11 - A7 H7 五、發明説明（9 ) 元件標號對照 1…記憶體用對偶晶片 2，2a...基板 3.. .樹脂 10.. .記憶體模組 11.. .基板用墊皮 12，32...通孔 13.. .BGA用墊皮 14.. .晶片用墊皮 15.. .結合電線 21.. .塊形連接端子 31.. .外部連接端子 33.. .絕緣膠帶 (誚先閱讀背而之注意事項再填寫本頁y I 表· 經濟部中央標準局員工消費合作社印聚 本紙張尺度適用中國國家標準（CNS ) Λ4規枱（21〇Χ 297公# ) -12-P Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economy The paper size is applicable to China National Standards (CNS) Λ4 Regulations (210x297 public expense) -11-A7 H7 V. Description of the invention (9) Component label comparison 1 ... Dual memory Wafer 2, 2a ... Substrate 3 .. Resin 10 .. Memory module 11 .. Substrate for substrate 12, 32 ... Through hole 13 .. Substrate for BGA 14 ... Wafer Use a pad 15 ... Combined wires 21 ... Block connection terminals 31 ... External connection terminals 33 ... Insulation tape (诮 Please read the precautions on the back before filling this page. I Form · Central Ministry of Economy Standards Bureau Consumers' Cooperative Printed Paper This paper applies Chinese National Standards (CNS) Λ4 gauge (21〇 × 297 公 #) -12-