JP4962388B2 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JP4962388B2 JP4962388B2 JP2008101134A JP2008101134A JP4962388B2 JP 4962388 B2 JP4962388 B2 JP 4962388B2 JP 2008101134 A JP2008101134 A JP 2008101134A JP 2008101134 A JP2008101134 A JP 2008101134A JP 4962388 B2 JP4962388 B2 JP 4962388B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- wiring board
- prepreg
- yarn
- yarns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
図1(a)は、本発明の第1実施形態に係るモールドパッケージ200の配線基板100への実装状態を示す概略平面図であり、図1(b)は(a)中の一点鎖線C−Cに沿った部分の概略断面図である。
図9(a)は、本発明の第2実施形態に係るモールドパッケージにおける配線基板との対向面の部分構成を示す概略平面図であり、図9(b)は、本実施形態の配線基板における電極20部分の構成を拡大して示す概略平面図である。
なお、上記図3に示される例では、1個の電極20は、上記格子状パターンにおける矩形状の隙間を通って、隣り合うヤーン11、12同士にまたがって配置されたものとなっていた。しかしながら、1個の電極20全体が1本のヤーンのみの上に位置せずに、1個の電極20の一部が1本のヤーンからはみ出して、当該隙間に位置していれば、上記第1実施形態の効果が発揮できる。
11 第1のヤーン
12 第2のヤーン
13 ガラスクロス
14 樹脂
20 電極
Claims (2)
- 第1の方向に沿って延びるガラス繊維よりなる複数本の第1のヤーン(11)と前記第1の方向に直交する第2の方向に沿って延びるガラス繊維よりなる複数本の第2のヤーン(12)とが交差するように格子状パターンにて織られてなるガラスクロス(13)に、樹脂(14)を含浸してなるプリプレグ(10)と、
前記プリプレグ(10)の表面に設けられたはんだ付け用の電極(20)とを備える配線基板において、
前記電極(20)は、前記第1の方向および前記第2の方向の両方向に対して斜めの方向に延びる形状となっていることにより、1個の前記電極(20)の一部が前記プリプレグ(10)の格子状パターンにおける隙間の直上に配置されており、
前記1個の電極(20)は、当該電極(20)の延びる方向と直交する方向の寸法である幅が、前記第1のヤーン(11)の幅および前記第2のヤーン(12)の幅と同等以下の大きさであることを特徴とする配線基板。 - 前記1個の電極(20)は、隣り合う前記ヤーン(11、12)同士にまたがって配置されたものとなっていることを特徴とする請求項1に記載の配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008101134A JP4962388B2 (ja) | 2008-04-09 | 2008-04-09 | 配線基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008101134A JP4962388B2 (ja) | 2008-04-09 | 2008-04-09 | 配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009253132A JP2009253132A (ja) | 2009-10-29 |
JP4962388B2 true JP4962388B2 (ja) | 2012-06-27 |
Family
ID=41313526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008101134A Active JP4962388B2 (ja) | 2008-04-09 | 2008-04-09 | 配線基板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4962388B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013140812A1 (ja) * | 2012-03-22 | 2013-09-26 | パナソニック株式会社 | ガラスクロス及びその製造方法、プリプレグ及びその製造方法、積層板、プリント配線板 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07147479A (ja) * | 1993-11-25 | 1995-06-06 | Kokusai Electric Co Ltd | 印刷配線基板用導電箔 |
JPH08139424A (ja) * | 1994-11-10 | 1996-05-31 | Ibiden Co Ltd | プリント配線板及びその製造方法 |
JPH10117048A (ja) * | 1996-10-09 | 1998-05-06 | Tec Corp | プリント基板 |
-
2008
- 2008-04-09 JP JP2008101134A patent/JP4962388B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2009253132A (ja) | 2009-10-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5400094B2 (ja) | 半導体パッケージ及びその実装方法 | |
JP2012104790A (ja) | 半導体装置 | |
JP2001339043A (ja) | 半導体装置及びそれを用いた半導体モジュール | |
JP4291209B2 (ja) | 半導体装置の製造方法 | |
JP6423685B2 (ja) | 電子部品、モジュール及びカメラ | |
JP5255009B2 (ja) | 半導体装置 | |
KR20170014958A (ko) | 반도체 패키지 및 반도체 패키지의 제조방법 | |
JP2009194079A (ja) | 半導体装置用配線基板とその製造方法及びそれを用いた半導体装置 | |
WO2012108469A1 (ja) | 半導体装置および半導体装置の製造方法 | |
JP4962388B2 (ja) | 配線基板 | |
JP2008270301A (ja) | 半導体装置 | |
JP5776373B2 (ja) | 電子装置 | |
JP2006190834A (ja) | 半導体パッケージ及びフレキシブルサーキット基板 | |
JP2015146404A (ja) | 半導体装置およびその製造方法 | |
JP4976767B2 (ja) | 積層形半導体装置 | |
JP2007141947A (ja) | 半導体装置およびその製造方法 | |
JP2004363224A (ja) | 半導体チップの接続構造 | |
JP2008147427A (ja) | 電子部品装置及び電子部品の実装方法 | |
JP4523425B2 (ja) | 半導体素子搭載用基板 | |
JP2006041224A (ja) | 電子装置および電子装置の実装構造 | |
JP2019508908A (ja) | はんだボールを備えたパッケージング構造、及びパッケージング構造を製造する方法 | |
JP2008091734A (ja) | 半導体装置およびその製造方法 | |
JP4377729B2 (ja) | 配線基板 | |
JP6396019B2 (ja) | 圧電発振器の製造方法 | |
JP5607782B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100607 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111130 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111206 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120123 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120228 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120312 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 4962388 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150406 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |