JP4911976B2 - ノード・キャパシタンスを増加した半導体メモリ・デバイス - Google Patents
ノード・キャパシタンスを増加した半導体メモリ・デバイス Download PDFInfo
- Publication number
- JP4911976B2 JP4911976B2 JP2005512855A JP2005512855A JP4911976B2 JP 4911976 B2 JP4911976 B2 JP 4911976B2 JP 2005512855 A JP2005512855 A JP 2005512855A JP 2005512855 A JP2005512855 A JP 2005512855A JP 4911976 B2 JP4911976 B2 JP 4911976B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- substrate
- layer
- gate
- finfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims description 33
- 230000000694 effects Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Description
Claims (11)
- 基板(112)と、
前記基板の第1の部分(114a)を覆い、前記基板の第2の部分(130)には存在しない第1の誘電体層(116,316)と、
前記第1の誘電体層とは異なる特性を有し、前記基板の前記第2の部分(130)を少なくとも部分的に覆うと共に、前記第1の誘電体層(116,316)またはフィンの両側に形成されたゲート誘電体層の一方(426)に連続する第2の誘電体層(132)と、
前記第1の誘電体層上の第1のドープ領域内に形成されたソース領域(118)と、
前記第1の誘電体層上の第2のドープ領域内に形成されたドレイン領域(120)と、
前記第2の誘電体層の上で前記第1のドープ領域と前記第2のドープ領域との間に形成されたゲート(128)と、
を有し、
前記第2の誘電体層により前記ゲートが前記基板に容量結合されて、前記基板上の前記第1の誘電体層の上に形成されたゲートの理論キャパシタンスより大きな前記基板に対する前記ゲートのゲート・キャパシタンスが提供される、集積回路半導体メモリ・デバイス(100)。 - 前記デバイスがRAMである、請求項1に記載のデバイス。
- 前記デバイスがSRAMである、請求項1に記載のデバイス。
- 前記デバイスがFETを含む、請求項1に記載のデバイス。
- 前記FETがFinFETである、請求項4に記載のデバイス。
- 前記第1の誘電体層が埋め込み酸化物層(116)であり、前記第2の誘電体層が前記埋め込み酸化物層より低い絶縁効果を提供する酸化物層(132)であり、請求項1または請求項5に記載のデバイス。
- 前記FinFETのフィン(122)が前記埋め込み酸化物層の上に形成される、請求項6に記載のデバイス。
- 前記第2の誘電体層が前記ゲート誘電体層より漏れが少ない、請求項1または請求項5に記載のデバイス。
- 前記基板が、上位レベルの上向きの第1の表面(314a)と、下位レベルの上向きの第2の表面(314b)とを有し、前記第1の誘電体層が前記第1の表面上に形成された誘電体層であり、前記第2の誘電体層が前記第2の表面上に形成された誘電体層であり、前記FinFETのフィン(322)が埋め込み層の上に形成される、請求項1または請求項5に記載のデバイス。
- 前記第1の誘電体層が埋め込み酸化物層(316)であり、前記第2の誘電体層が酸化物層(332a、332b)である、請求項9に記載のデバイス。
- 前記第1の誘電体層が埋め込み酸化物層(116)であり、前記第2の誘電体層が薄い酸化物層(132)である、請求項8に記載のデバイス。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2003/039026 WO2005064682A1 (en) | 2003-12-08 | 2003-12-08 | Semiconductor memory device with increased node capacitance |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007521640A JP2007521640A (ja) | 2007-08-02 |
JP4911976B2 true JP4911976B2 (ja) | 2012-04-04 |
Family
ID=34738253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005512855A Expired - Fee Related JP4911976B2 (ja) | 2003-12-08 | 2003-12-08 | ノード・キャパシタンスを増加した半導体メモリ・デバイス |
Country Status (7)
Country | Link |
---|---|
US (1) | US7352025B2 (ja) |
EP (1) | EP1692724B1 (ja) |
JP (1) | JP4911976B2 (ja) |
KR (1) | KR100935988B1 (ja) |
CN (1) | CN100546042C (ja) |
AU (1) | AU2003297751A1 (ja) |
WO (1) | WO2005064682A1 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006049627A (ja) * | 2004-08-05 | 2006-02-16 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100555569B1 (ko) | 2004-08-06 | 2006-03-03 | 삼성전자주식회사 | 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법 |
US7470951B2 (en) * | 2005-01-31 | 2008-12-30 | Freescale Semiconductor, Inc. | Hybrid-FET and its application as SRAM |
KR100645065B1 (ko) * | 2005-06-23 | 2006-11-10 | 삼성전자주식회사 | 핀 전계 효과 트랜지스터와 이를 구비하는 비휘발성 메모리장치 및 그 형성 방법 |
US8513066B2 (en) * | 2005-10-25 | 2013-08-20 | Freescale Semiconductor, Inc. | Method of making an inverted-T channel transistor |
US7452768B2 (en) | 2005-10-25 | 2008-11-18 | Freescale Semiconductor, Inc. | Multiple device types including an inverted-T channel transistor and method therefor |
US7323373B2 (en) * | 2006-01-25 | 2008-01-29 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device with decreased undercutting of semiconductor material |
US20090020792A1 (en) * | 2007-07-18 | 2009-01-22 | Rafael Rios | Isolated tri-gate transistor fabricated on bulk substrate |
US8912602B2 (en) * | 2009-04-14 | 2014-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs and methods for forming the same |
US8158500B2 (en) | 2010-01-27 | 2012-04-17 | International Business Machines Corporation | Field effect transistors (FETS) and methods of manufacture |
US8778744B2 (en) | 2011-06-24 | 2014-07-15 | Institute of Microelectronics, Chinese Academy of Sciences | Method for manufacturing semiconductor field effect transistor |
CN102842507B (zh) * | 2011-06-24 | 2015-08-19 | 中国科学院微电子研究所 | 半导体场效应晶体管的制备方法 |
US9087743B2 (en) * | 2013-11-20 | 2015-07-21 | Globalfoundries Inc. | Silicon-on-insulator finFET with bulk source and drain |
US9741810B2 (en) * | 2014-07-30 | 2017-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel of gate-all-around transistor |
US9508741B2 (en) | 2015-02-10 | 2016-11-29 | International Business Machines Corporation | CMOS structure on SSOI wafer |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283700A (ja) * | 1991-05-27 | 1993-10-29 | Nec Corp | 半導体装置 |
JPH06291283A (ja) * | 1993-04-05 | 1994-10-18 | Nec Corp | 半導体記憶装置 |
JPH07161843A (ja) * | 1993-12-10 | 1995-06-23 | Sony Corp | Sram装置 |
JPH07183400A (ja) * | 1993-12-22 | 1995-07-21 | Nec Corp | 半導体記憶装置 |
JPH09270469A (ja) * | 1996-03-29 | 1997-10-14 | Sanyo Electric Co Ltd | 半導体メモリ装置 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3387286A (en) | 1967-07-14 | 1968-06-04 | Ibm | Field-effect transistor memory |
US5346834A (en) * | 1988-11-21 | 1994-09-13 | Hitachi, Ltd. | Method for manufacturing a semiconductor device and a semiconductor memory device |
JP3460863B2 (ja) * | 1993-09-17 | 2003-10-27 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5446621A (en) | 1994-04-28 | 1995-08-29 | Wandel & Goltermann Ate Systems Ltd. | Platform module system for a larger electronic system |
JP3535615B2 (ja) | 1995-07-18 | 2004-06-07 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6130470A (en) | 1997-03-24 | 2000-10-10 | Advanced Micro Devices, Inc. | Static random access memory cell having buried sidewall capacitors between storage nodes |
US5831899A (en) | 1997-04-07 | 1998-11-03 | Integrated Device Technology, Inc. | Local interconnect structure and process for six-transistor SRAM cell |
US6165849A (en) | 1998-12-04 | 2000-12-26 | Advanced Micro Devices, Inc. | Method of manufacturing mosfet with differential gate oxide thickness on the same IC chip |
US6140171A (en) | 1999-01-20 | 2000-10-31 | International Business Machines Corporation | FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication |
US6359311B1 (en) * | 2001-01-17 | 2002-03-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same |
JP2002359298A (ja) | 2001-05-31 | 2002-12-13 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR100467527B1 (ko) * | 2001-06-21 | 2005-01-24 | 재단법인서울대학교산학협력재단 | 이중 게이트 mosfet 및 그 제조방법 |
US6661049B2 (en) | 2001-09-06 | 2003-12-09 | Taiwan Semiconductor Manufacturing Co., Ltd | Microelectronic capacitor structure embedded within microelectronic isolation region |
US6689650B2 (en) * | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US6551883B1 (en) | 2001-12-27 | 2003-04-22 | Silicon Integrated Systems Corp. | MOS device with dual gate insulators and method of forming the same |
US6583469B1 (en) * | 2002-01-28 | 2003-06-24 | International Business Machines Corporation | Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same |
US6974729B2 (en) * | 2002-07-16 | 2005-12-13 | Interuniversitair Microelektronica Centrum (Imec) | Integrated semiconductor fin device and a method for manufacturing such device |
JP4546021B2 (ja) * | 2002-10-02 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型電界効果型トランジスタ及び半導体装置 |
US7087499B2 (en) * | 2002-12-20 | 2006-08-08 | International Business Machines Corporation | Integrated antifuse structure for FINFET and CMOS devices |
US7074656B2 (en) * | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
US6992354B2 (en) * | 2003-06-25 | 2006-01-31 | International Business Machines Corporation | FinFET having suppressed parasitic device characteristics |
US6909151B2 (en) * | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7183182B2 (en) * | 2003-09-24 | 2007-02-27 | International Business Machines Corporation | Method and apparatus for fabricating CMOS field effect transistors |
US6962843B2 (en) * | 2003-11-05 | 2005-11-08 | International Business Machines Corporation | Method of fabricating a finfet |
-
2003
- 2003-12-08 US US10/596,029 patent/US7352025B2/en not_active Expired - Lifetime
- 2003-12-08 EP EP03796818A patent/EP1692724B1/en not_active Expired - Lifetime
- 2003-12-08 KR KR1020067010819A patent/KR100935988B1/ko not_active IP Right Cessation
- 2003-12-08 JP JP2005512855A patent/JP4911976B2/ja not_active Expired - Fee Related
- 2003-12-08 CN CNB200380110735XA patent/CN100546042C/zh not_active Expired - Fee Related
- 2003-12-08 WO PCT/US2003/039026 patent/WO2005064682A1/en active Application Filing
- 2003-12-08 AU AU2003297751A patent/AU2003297751A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283700A (ja) * | 1991-05-27 | 1993-10-29 | Nec Corp | 半導体装置 |
JPH06291283A (ja) * | 1993-04-05 | 1994-10-18 | Nec Corp | 半導体記憶装置 |
JPH07161843A (ja) * | 1993-12-10 | 1995-06-23 | Sony Corp | Sram装置 |
JPH07183400A (ja) * | 1993-12-22 | 1995-07-21 | Nec Corp | 半導体記憶装置 |
JPH09270469A (ja) * | 1996-03-29 | 1997-10-14 | Sanyo Electric Co Ltd | 半導体メモリ装置 |
Also Published As
Publication number | Publication date |
---|---|
KR100935988B1 (ko) | 2010-01-08 |
EP1692724A1 (en) | 2006-08-23 |
EP1692724B1 (en) | 2012-06-13 |
KR20060121124A (ko) | 2006-11-28 |
JP2007521640A (ja) | 2007-08-02 |
US20070085134A1 (en) | 2007-04-19 |
US7352025B2 (en) | 2008-04-01 |
CN100546042C (zh) | 2009-09-30 |
AU2003297751A1 (en) | 2005-07-21 |
CN1879219A (zh) | 2006-12-13 |
WO2005064682A1 (en) | 2005-07-14 |
EP1692724A4 (en) | 2007-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11398493B2 (en) | Arrays of memory cells including pairs of memory cells having respective charge storage nodes between respective access lines | |
US6646300B2 (en) | Semiconductor memory device | |
JP4911976B2 (ja) | ノード・キャパシタンスを増加した半導体メモリ・デバイス | |
US8502318B2 (en) | SRAM memory cell provided with transistors having a vertical multichannel structure | |
US20110133263A1 (en) | Semiconductor device having reduced sub-threshold leakage | |
US6281088B1 (en) | Method of manufacturing SRAM having enhanced cell ratio | |
CN102171813B (zh) | 具有独立源漏设计的三栅静态随机存取存储器及由其制成的器件 | |
US20080224196A1 (en) | Semiconductor device and manufacturing process for the same | |
JP4429798B2 (ja) | フィン型チャネルfetを用いたシステムlsi及びその製造方法 | |
EP0821412B1 (en) | Hemispherical-grained silicon top-gate electrode for improved soft-error immunity in SRAMs | |
TWI453868B (zh) | 記憶體陣列、半導體結構與電子系統,以及形成記憶體陣列、半導體結構與電子系統之方法 | |
JP2022140387A (ja) | 単一半導体ダイにおけるモノリシック集積および/または不均一集積の最適化のための統合スケーリングおよびストレッチングプラットフォーム | |
JPH10223779A (ja) | 異なるゲートキャパシタンスを有する絶縁ゲート電界効果トランジスタを備えた集積回路及びその形成方法 | |
US5170372A (en) | Memory device having bit lines over a field oxide | |
US20120045872A1 (en) | Semiconductor Memory Device | |
JPH04256359A (ja) | 集積回路メモリ装置 | |
KR960014465B1 (ko) | 스태틱 램 셀 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090616 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101214 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20101228 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20101228 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110218 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111227 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20111227 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120117 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4911976 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150127 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |