JP4910319B2 - インターフェース回路を内蔵した集積回路装置及び電子機器 - Google Patents

インターフェース回路を内蔵した集積回路装置及び電子機器 Download PDF

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Publication number
JP4910319B2
JP4910319B2 JP2005197930A JP2005197930A JP4910319B2 JP 4910319 B2 JP4910319 B2 JP 4910319B2 JP 2005197930 A JP2005197930 A JP 2005197930A JP 2005197930 A JP2005197930 A JP 2005197930A JP 4910319 B2 JP4910319 B2 JP 4910319B2
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JP
Japan
Prior art keywords
input
power supply
differential signal
pad
input pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2005197930A
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English (en)
Japanese (ja)
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JP2007019185A (ja
JP2007019185A5 (https=
Inventor
史和 小松
安成 降矢
公徳 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2005197930A priority Critical patent/JP4910319B2/ja
Priority to US11/426,119 priority patent/US7432732B2/en
Publication of JP2007019185A publication Critical patent/JP2007019185A/ja
Publication of JP2007019185A5 publication Critical patent/JP2007019185A5/ja
Application granted granted Critical
Publication of JP4910319B2 publication Critical patent/JP4910319B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423—Shielding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/223—Differential pair signal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2005197930A 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器 Expired - Lifetime JP4910319B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005197930A JP4910319B2 (ja) 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器
US11/426,119 US7432732B2 (en) 2005-07-06 2006-06-23 Integrated circuit device including interface circuit and electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005197930A JP4910319B2 (ja) 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器

Publications (3)

Publication Number Publication Date
JP2007019185A JP2007019185A (ja) 2007-01-25
JP2007019185A5 JP2007019185A5 (https=) 2008-08-14
JP4910319B2 true JP4910319B2 (ja) 2012-04-04

Family

ID=37617753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005197930A Expired - Lifetime JP4910319B2 (ja) 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器

Country Status (2)

Country Link
US (1) US7432732B2 (https=)
JP (1) JP4910319B2 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4434288B2 (ja) * 2008-03-19 2010-03-17 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
JP4434289B2 (ja) * 2008-03-19 2010-03-17 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
US7741871B2 (en) * 2008-03-19 2010-06-22 Seiko Epson Corporation Integrated circuit device, electro-optical device, and electronic instrument
JP4544326B2 (ja) * 2008-03-26 2010-09-15 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
JP5151604B2 (ja) * 2008-03-26 2013-02-27 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
KR101728550B1 (ko) * 2010-11-26 2017-04-19 엘지이노텍 주식회사 전자기간섭 노이즈 저감회로
JP6194372B2 (ja) * 2014-01-22 2017-09-06 アルプス電気株式会社 センサモジュール、並びに、これに用いるセンサチップ及び処理回路チップ
TWI724059B (zh) * 2016-07-08 2021-04-11 日商半導體能源研究所股份有限公司 顯示裝置、顯示模組及電子機器
JP7394760B2 (ja) 2018-07-20 2023-12-08 株式会社半導体エネルギー研究所 受信回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04118946A (ja) * 1990-09-10 1992-04-20 Toshiba Corp 半導体集積回路装置
US6002268A (en) * 1993-01-08 1999-12-14 Dynachip Corporation FPGA with conductors segmented by active repeaters
US6625795B1 (en) * 1998-06-29 2003-09-23 Xilinx, Inc. Method and apparatus for placement of input-output design objects into a programmable gate array
JP4034915B2 (ja) * 1999-09-22 2008-01-16 株式会社ルネサステクノロジ 半導体チップおよび液晶表示装置
JP2001144091A (ja) 1999-11-11 2001-05-25 Sanyo Electric Co Ltd 半導体集積回路
JP3858572B2 (ja) 2000-08-03 2006-12-13 セイコーエプソン株式会社 電気光学装置

Also Published As

Publication number Publication date
JP2007019185A (ja) 2007-01-25
US7432732B2 (en) 2008-10-07
US20070008005A1 (en) 2007-01-11

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