JP4910319B2 - インターフェース回路を内蔵した集積回路装置及び電子機器 - Google Patents

インターフェース回路を内蔵した集積回路装置及び電子機器 Download PDF

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Publication number
JP4910319B2
JP4910319B2 JP2005197930A JP2005197930A JP4910319B2 JP 4910319 B2 JP4910319 B2 JP 4910319B2 JP 2005197930 A JP2005197930 A JP 2005197930A JP 2005197930 A JP2005197930 A JP 2005197930A JP 4910319 B2 JP4910319 B2 JP 4910319B2
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Japan
Prior art keywords
input
power supply
differential signal
pad
input pad
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Expired - Lifetime
Application number
JP2005197930A
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English (en)
Japanese (ja)
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JP2007019185A (ja
JP2007019185A5 (enExample
Inventor
史和 小松
安成 降矢
公徳 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
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Seiko Epson Corp
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Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2005197930A priority Critical patent/JP4910319B2/ja
Priority to US11/426,119 priority patent/US7432732B2/en
Publication of JP2007019185A publication Critical patent/JP2007019185A/ja
Publication of JP2007019185A5 publication Critical patent/JP2007019185A5/ja
Application granted granted Critical
Publication of JP4910319B2 publication Critical patent/JP4910319B2/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225Shielding layers formed together with wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6638Differential pair signal lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01037Rubidium [Rb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01066Dysprosium [Dy]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1905Shape
    • H01L2924/19051Impedance matching structure [e.g. balun]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2005197930A 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器 Expired - Lifetime JP4910319B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005197930A JP4910319B2 (ja) 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器
US11/426,119 US7432732B2 (en) 2005-07-06 2006-06-23 Integrated circuit device including interface circuit and electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005197930A JP4910319B2 (ja) 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器

Publications (3)

Publication Number Publication Date
JP2007019185A JP2007019185A (ja) 2007-01-25
JP2007019185A5 JP2007019185A5 (enExample) 2008-08-14
JP4910319B2 true JP4910319B2 (ja) 2012-04-04

Family

ID=37617753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005197930A Expired - Lifetime JP4910319B2 (ja) 2005-07-06 2005-07-06 インターフェース回路を内蔵した集積回路装置及び電子機器

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Country Link
US (1) US7432732B2 (enExample)
JP (1) JP4910319B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4434288B2 (ja) * 2008-03-19 2010-03-17 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
US7741871B2 (en) * 2008-03-19 2010-06-22 Seiko Epson Corporation Integrated circuit device, electro-optical device, and electronic instrument
JP4434289B2 (ja) * 2008-03-19 2010-03-17 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
JP5151604B2 (ja) * 2008-03-26 2013-02-27 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
JP4544326B2 (ja) * 2008-03-26 2010-09-15 セイコーエプソン株式会社 集積回路装置、電気光学装置及び電子機器
KR101728550B1 (ko) * 2010-11-26 2017-04-19 엘지이노텍 주식회사 전자기간섭 노이즈 저감회로
JP6194372B2 (ja) * 2014-01-22 2017-09-06 アルプス電気株式会社 センサモジュール、並びに、これに用いるセンサチップ及び処理回路チップ
TWI724059B (zh) * 2016-07-08 2021-04-11 日商半導體能源研究所股份有限公司 顯示裝置、顯示模組及電子機器
US11482155B2 (en) 2018-07-20 2022-10-25 Semiconductor Energy Laboratory Co., Ltd. Receiving circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04118946A (ja) * 1990-09-10 1992-04-20 Toshiba Corp 半導体集積回路装置
US6002268A (en) * 1993-01-08 1999-12-14 Dynachip Corporation FPGA with conductors segmented by active repeaters
US6625795B1 (en) * 1998-06-29 2003-09-23 Xilinx, Inc. Method and apparatus for placement of input-output design objects into a programmable gate array
JP4034915B2 (ja) * 1999-09-22 2008-01-16 株式会社ルネサステクノロジ 半導体チップおよび液晶表示装置
JP2001144091A (ja) 1999-11-11 2001-05-25 Sanyo Electric Co Ltd 半導体集積回路
JP3858572B2 (ja) 2000-08-03 2006-12-13 セイコーエプソン株式会社 電気光学装置

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Publication number Publication date
JP2007019185A (ja) 2007-01-25
US7432732B2 (en) 2008-10-07
US20070008005A1 (en) 2007-01-11

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