JP4903873B2 - 基板トレンチ内にスペーサから形成されたフローティングゲートを有する不揮発性メモリセルアレイおよびその作製方法 - Google Patents

基板トレンチ内にスペーサから形成されたフローティングゲートを有する不揮発性メモリセルアレイおよびその作製方法 Download PDF

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Publication number
JP4903873B2
JP4903873B2 JP2009529310A JP2009529310A JP4903873B2 JP 4903873 B2 JP4903873 B2 JP 4903873B2 JP 2009529310 A JP2009529310 A JP 2009529310A JP 2009529310 A JP2009529310 A JP 2009529310A JP 4903873 B2 JP4903873 B2 JP 4903873B2
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Prior art keywords
trenches
trench
volatile memory
gate
extending
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Expired - Fee Related
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JP2009529310A
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Japanese (ja)
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JP2010504644A5 (ja
JP2010504644A (ja
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モクレシー，ニーマ
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SanDisk Corp
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SanDisk Corp
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Priority claimed from US11/533,313 external-priority patent/US7646054B2/en
Priority claimed from US11/533,317 external-priority patent/US7696044B2/en
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Publication of JP2010504644A publication Critical patent/JP2010504644A/ja
Publication of JP2010504644A5 publication Critical patent/JP2010504644A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2009529310A 2006-09-19 2007-09-13 基板トレンチ内にスペーサから形成されたフローティングゲートを有する不揮発性メモリセルアレイおよびその作製方法 Expired - Fee Related JP4903873B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/533,313 US7646054B2 (en) 2006-09-19 2006-09-19 Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches
US11/533,317 2006-09-19
US11/533,313 2006-09-19
US11/533,317 US7696044B2 (en) 2006-09-19 2006-09-19 Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches
PCT/US2007/078420 WO2008036552A2 (en) 2006-09-19 2007-09-13 Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches

Publications (3)

Publication Number Publication Date
JP2010504644A JP2010504644A (ja) 2010-02-12
JP2010504644A5 JP2010504644A5 (ja) 2011-06-02
JP4903873B2 true JP4903873B2 (ja) 2012-03-28

Family

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JP2009529310A Expired - Fee Related JP4903873B2 (ja) 2006-09-19 2007-09-13 基板トレンチ内にスペーサから形成されたフローティングゲートを有する不揮発性メモリセルアレイおよびその作製方法

Country Status (5)

Country Link
EP (1) EP2064733A2 (ko)
JP (1) JP4903873B2 (ko)
KR (1) KR101427362B1 (ko)
TW (1) TWI375331B (ko)
WO (1) WO2008036552A2 (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2010046997A1 (ja) * 2008-10-24 2012-03-15 株式会社アドバンテスト 電子デバイスおよび製造方法
TWI559459B (zh) * 2014-12-03 2016-11-21 力晶科技股份有限公司 快閃記憶體及其製造方法
US10141323B2 (en) 2016-01-04 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory and method of manufacturing the same
US10658479B2 (en) * 2017-11-15 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Flash memory cell structure with step-shaped floating gate
CN110010606B (zh) * 2018-01-05 2023-04-07 硅存储技术公司 衬底沟槽中具有浮栅的双位非易失性存储器单元
JP6623247B2 (ja) * 2018-04-09 2019-12-18 ウィンボンド エレクトロニクス コーポレーション フラッシュメモリおよびその製造方法

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US5656544A (en) * 1992-03-12 1997-08-12 International Business Machines Corporation Process for forming a polysilicon electrode in a trench
US5705415A (en) * 1994-10-04 1998-01-06 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
US5998261A (en) * 1995-07-05 1999-12-07 Siemens Aktiengesellschaft Method of producing a read-only storage cell arrangement
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
JP2001077219A (ja) * 1999-06-29 2001-03-23 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
JP2002198447A (ja) * 2000-11-15 2002-07-12 Hynix Semiconductor Inc 非揮発性メモリの製造方法
US20030185073A1 (en) * 2002-03-28 2003-10-02 Kim Jin-Woo Nonvolatile memory cells having split gate structure and methods of fabricating the same
JP2004356381A (ja) * 2003-05-29 2004-12-16 Innotech Corp 半導体記憶装置の製造方法
JP2004356660A (ja) * 2004-09-17 2004-12-16 Semiconductor Energy Lab Co Ltd 半導体装置
US20050087796A1 (en) * 2003-10-23 2005-04-28 Jung Jin H. Flash memory and methods of fabricating the same
US20050151185A1 (en) * 2003-12-31 2005-07-14 Jung Jin H. Semiconductor device and fabricating method thereof
JP2005260202A (ja) * 2004-02-13 2005-09-22 Innotech Corp 半導体記憶装置及びその製造方法
US6952034B2 (en) * 2002-04-05 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried source line and floating gate
US20060033144A1 (en) * 2004-08-11 2006-02-16 Micron Technology, Inc. Non-planar flash memory array with shielded floating gates on silicon mesas
US7049652B2 (en) * 2003-12-10 2006-05-23 Sandisk Corporation Pillar cell flash memory technology
US20060220093A1 (en) * 2002-12-19 2006-10-05 Koninklijke Philips Electronics N.V. Non-volatile memory cell and method of fabrication
JP2006332640A (ja) * 2005-05-20 2006-12-07 Silicon Storage Technology Inc 双方向分割ゲートｎａｎｄフラッシュメモリ構造及びアレイ、そのプログラミング方法、消去方法及び読み出し方法、並びに、製造方法
US20070032025A1 (en) * 2004-03-08 2007-02-08 Interuniversitair Microelektronica Centrum (Imec) Method for forming germanides and devices obtained thereof
US20070034963A1 (en) * 2005-08-10 2007-02-15 Toshiba America Electronic Components, Inc. Semiconductor device with close stress liner film and method of manufacturing the same
US20070141780A1 (en) * 2005-12-21 2007-06-21 Masaaki Higashitani Methods of forming flash devices with shared word lines
US7250340B2 (en) * 2005-07-25 2007-07-31 Freescale Semiconductor, Inc. Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench

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US5411905A (en) * 1994-04-29 1995-05-02 International Business Machines Corporation Method of making trench EEPROM structure on SOI with dual channels
JPH10112511A (ja) * 1996-10-07 1998-04-28 Ricoh Co Ltd 半導体不揮発性メモリ及びその製造方法
US5929477A (en) * 1997-01-22 1999-07-27 International Business Machines Corporation Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
US6103573A (en) * 1999-06-30 2000-08-15 Sandisk Corporation Processing techniques for making a dual floating gate EEPROM cell array
AU2003263748A1 (en) * 2002-06-21 2004-01-06 Micron Technology, Inc. Nrom memory cell, memory array, related devices and methods
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US6815758B1 (en) * 2003-08-22 2004-11-09 Powerchip Semiconductor Corp. Flash memory cell
US6906379B2 (en) * 2003-08-28 2005-06-14 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried floating gate

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Publication number Priority date Publication date Assignee Title
US5656544A (en) * 1992-03-12 1997-08-12 International Business Machines Corporation Process for forming a polysilicon electrode in a trench
US5705415A (en) * 1994-10-04 1998-01-06 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
US5998261A (en) * 1995-07-05 1999-12-07 Siemens Aktiengesellschaft Method of producing a read-only storage cell arrangement
JP2001077219A (ja) * 1999-06-29 2001-03-23 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
JP2002198447A (ja) * 2000-11-15 2002-07-12 Hynix Semiconductor Inc 非揮発性メモリの製造方法
US20030185073A1 (en) * 2002-03-28 2003-10-02 Kim Jin-Woo Nonvolatile memory cells having split gate structure and methods of fabricating the same
US6952034B2 (en) * 2002-04-05 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried source line and floating gate
US20060220093A1 (en) * 2002-12-19 2006-10-05 Koninklijke Philips Electronics N.V. Non-volatile memory cell and method of fabrication
JP2004356381A (ja) * 2003-05-29 2004-12-16 Innotech Corp 半導体記憶装置の製造方法
US20050087796A1 (en) * 2003-10-23 2005-04-28 Jung Jin H. Flash memory and methods of fabricating the same
US7049652B2 (en) * 2003-12-10 2006-05-23 Sandisk Corporation Pillar cell flash memory technology
US20050151185A1 (en) * 2003-12-31 2005-07-14 Jung Jin H. Semiconductor device and fabricating method thereof
JP2005260202A (ja) * 2004-02-13 2005-09-22 Innotech Corp 半導体記憶装置及びその製造方法
US20070032025A1 (en) * 2004-03-08 2007-02-08 Interuniversitair Microelektronica Centrum (Imec) Method for forming germanides and devices obtained thereof
US20060033144A1 (en) * 2004-08-11 2006-02-16 Micron Technology, Inc. Non-planar flash memory array with shielded floating gates on silicon mesas
JP2004356660A (ja) * 2004-09-17 2004-12-16 Semiconductor Energy Lab Co Ltd 半導体装置
JP2006332640A (ja) * 2005-05-20 2006-12-07 Silicon Storage Technology Inc 双方向分割ゲートｎａｎｄフラッシュメモリ構造及びアレイ、そのプログラミング方法、消去方法及び読み出し方法、並びに、製造方法
US7250340B2 (en) * 2005-07-25 2007-07-31 Freescale Semiconductor, Inc. Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench
US20070034963A1 (en) * 2005-08-10 2007-02-15 Toshiba America Electronic Components, Inc. Semiconductor device with close stress liner film and method of manufacturing the same
US20070141780A1 (en) * 2005-12-21 2007-06-21 Masaaki Higashitani Methods of forming flash devices with shared word lines

Also Published As

Publication number Publication date
KR20090075807A (ko) 2009-07-09
TW200828597A (en) 2008-07-01
KR101427362B1 (ko) 2014-08-07
EP2064733A2 (en) 2009-06-03
WO2008036552A3 (en) 2008-09-12
WO2008036552A2 (en) 2008-03-27
TWI375331B (en) 2012-10-21
JP2010504644A (ja) 2010-02-12

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