WO2008036552A3 - Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches - Google Patents

Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches Download PDF

Info

Publication number
WO2008036552A3
WO2008036552A3 PCT/US2007/078420 US2007078420W WO2008036552A3 WO 2008036552 A3 WO2008036552 A3 WO 2008036552A3 US 2007078420 W US2007078420 W US 2007078420W WO 2008036552 A3 WO2008036552 A3 WO 2008036552A3
Authority
WO
WIPO (PCT)
Prior art keywords
array
memory cells
spacers
volatile memory
substrate trenches
Prior art date
Application number
PCT/US2007/078420
Other languages
French (fr)
Other versions
WO2008036552A2 (en
Inventor
Nima Mokhlesi
Original Assignee
Sandisk Corp
Nima Mokhlesi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/533,317 external-priority patent/US7696044B2/en
Priority claimed from US11/533,313 external-priority patent/US7646054B2/en
Application filed by Sandisk Corp, Nima Mokhlesi filed Critical Sandisk Corp
Priority to JP2009529310A priority Critical patent/JP4903873B2/en
Priority to EP07842450A priority patent/EP2064733A2/en
Priority to CN2007800343669A priority patent/CN101517707B/en
Priority to KR1020097006107A priority patent/KR101427362B1/en
Publication of WO2008036552A2 publication Critical patent/WO2008036552A2/en
Publication of WO2008036552A3 publication Critical patent/WO2008036552A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements (103, 105, 111, 113) are positioned along sidewalls of substrate trenches (60, 61), preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.
PCT/US2007/078420 2006-09-19 2007-09-13 Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches WO2008036552A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009529310A JP4903873B2 (en) 2006-09-19 2007-09-13 Nonvolatile memory cell array having floating gate formed from spacers in substrate trench and method for manufacturing the same
EP07842450A EP2064733A2 (en) 2006-09-19 2007-09-13 Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches
CN2007800343669A CN101517707B (en) 2006-09-19 2007-09-13 Non-volatile memory and method for forming non-volatile memory unit array
KR1020097006107A KR101427362B1 (en) 2006-09-19 2007-09-13 Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/533,317 US7696044B2 (en) 2006-09-19 2006-09-19 Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches
US11/533,313 2006-09-19
US11/533,317 2006-09-19
US11/533,313 US7646054B2 (en) 2006-09-19 2006-09-19 Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches

Publications (2)

Publication Number Publication Date
WO2008036552A2 WO2008036552A2 (en) 2008-03-27
WO2008036552A3 true WO2008036552A3 (en) 2008-09-12

Family

ID=39106139

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/078420 WO2008036552A2 (en) 2006-09-19 2007-09-13 Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches

Country Status (5)

Country Link
EP (1) EP2064733A2 (en)
JP (1) JP4903873B2 (en)
KR (1) KR101427362B1 (en)
TW (1) TWI375331B (en)
WO (1) WO2008036552A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110042188A (en) * 2008-10-24 2011-04-25 가부시키가이샤 어드밴티스트 Electronic device and method for manufacturing the same
TWI559459B (en) * 2014-12-03 2016-11-21 力晶科技股份有限公司 Flash memory and manufacturing method thereof
US10141323B2 (en) * 2016-01-04 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory and method of manufacturing the same
US10658479B2 (en) * 2017-11-15 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Flash memory cell structure with step-shaped floating gate
CN110010606B (en) * 2018-01-05 2023-04-07 硅存储技术公司 Dual bit non-volatile memory cell with floating gate in substrate trench
JP6623247B2 (en) * 2018-04-09 2019-12-18 ウィンボンド エレクトロニクス コーポレーション Flash memory and manufacturing method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5705415A (en) * 1994-10-04 1998-01-06 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
US6103573A (en) * 1999-06-30 2000-08-15 Sandisk Corporation Processing techniques for making a dual floating gate EEPROM cell array
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
US20030185073A1 (en) * 2002-03-28 2003-10-02 Kim Jin-Woo Nonvolatile memory cells having split gate structure and methods of fabricating the same
US6815758B1 (en) * 2003-08-22 2004-11-09 Powerchip Semiconductor Corp. Flash memory cell
US20050045940A1 (en) * 2003-08-28 2005-03-03 Bomy Chen Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, and a memory array made thereby
US20050087796A1 (en) * 2003-10-23 2005-04-28 Jung Jin H. Flash memory and methods of fabricating the same
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399516A (en) * 1992-03-12 1995-03-21 International Business Machines Corporation Method of making shadow RAM cell having a shallow trench EEPROM
US5386132A (en) * 1992-11-02 1995-01-31 Wong; Chun C. D. Multimedia storage system with highly compact memory device
US5411905A (en) * 1994-04-29 1995-05-02 International Business Machines Corporation Method of making trench EEPROM structure on SOI with dual channels
DE19524478C2 (en) * 1995-07-05 2002-03-14 Infineon Technologies Ag Method for producing a read-only memory cell arrangement
JPH10112511A (en) * 1996-10-07 1998-04-28 Ricoh Co Ltd Semiconductor nonvolatile storage device and its manufacture
US5929477A (en) * 1997-01-22 1999-07-27 International Business Machines Corporation Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
US5973356A (en) * 1997-07-08 1999-10-26 Micron Technology, Inc. Ultra high density flash memory
JP2001077219A (en) * 1999-06-29 2001-03-23 Toshiba Corp Nonvolatile semiconductor storage device and manufacture thereof
KR100364803B1 (en) * 2000-11-15 2002-12-16 주식회사 하이닉스반도체 Method for manufacturing Nonvolatile Memory
US6952034B2 (en) * 2002-04-05 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried source line and floating gate
JP4678760B2 (en) * 2002-06-21 2011-04-27 マイクロン テクノロジー， インク． Array of memory cells, memory array, memory device, and method of forming a memory array having multi-state cells
CN1729558A (en) * 2002-12-19 2006-02-01 皇家飞利浦电子股份有限公司 Vertical split gate non-volatile memory cell and method of fabrication thereof
JP2004356381A (en) * 2003-05-29 2004-12-16 Innotech Corp Method of manufacturing semiconductor storage device
US7049652B2 (en) * 2003-12-10 2006-05-23 Sandisk Corporation Pillar cell flash memory technology
KR100526478B1 (en) * 2003-12-31 2005-11-08 동부아남반도체 주식회사 Semiconductor device and fabricating method thereof
JP4557678B2 (en) * 2004-02-13 2010-10-06 イノテック株式会社 Semiconductor memory device
US7517765B2 (en) * 2004-03-08 2009-04-14 Interuniversitair Microelektronica Centrum (Imec) Method for forming germanides and devices obtained thereof
US7388251B2 (en) * 2004-08-11 2008-06-17 Micron Technology, Inc. Non-planar flash memory array with shielded floating gates on silicon mesas
JP4209824B2 (en) * 2004-09-17 2009-01-14 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7247907B2 (en) * 2005-05-20 2007-07-24 Silicon Storage Technology, Inc. Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
US7250340B2 (en) * 2005-07-25 2007-07-31 Freescale Semiconductor, Inc. Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench
US7569888B2 (en) * 2005-08-10 2009-08-04 Toshiba America Electronic Components, Inc. Semiconductor device with close stress liner film and method of manufacturing the same
US7655536B2 (en) * 2005-12-21 2010-02-02 Sandisk Corporation Methods of forming flash devices with shared word lines

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5705415A (en) * 1994-10-04 1998-01-06 Motorola, Inc. Process for forming an electrically programmable read-only memory cell
US6103573A (en) * 1999-06-30 2000-08-15 Sandisk Corporation Processing techniques for making a dual floating gate EEPROM cell array
US6151248A (en) * 1999-06-30 2000-11-21 Sandisk Corporation Dual floating gate EEPROM cell array with steering gates shared by adjacent cells
US6255689B1 (en) * 1999-12-20 2001-07-03 United Microelectronics Corp. Flash memory structure and method of manufacture
US20030185073A1 (en) * 2002-03-28 2003-10-02 Kim Jin-Woo Nonvolatile memory cells having split gate structure and methods of fabricating the same
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US6815758B1 (en) * 2003-08-22 2004-11-09 Powerchip Semiconductor Corp. Flash memory cell
US20050045940A1 (en) * 2003-08-28 2005-03-03 Bomy Chen Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate, and a memory array made thereby
US20050087796A1 (en) * 2003-10-23 2005-04-28 Jung Jin H. Flash memory and methods of fabricating the same

Also Published As

Publication number Publication date
WO2008036552A2 (en) 2008-03-27
JP2010504644A (en) 2010-02-12
TW200828597A (en) 2008-07-01
EP2064733A2 (en) 2009-06-03
KR20090075807A (en) 2009-07-09
KR101427362B1 (en) 2014-08-07
TWI375331B (en) 2012-10-21
JP4903873B2 (en) 2012-03-28

Similar Documents

Publication Publication Date Title
TW200605364A (en) An isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor
TW200802735A (en) Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element
TW200715537A (en) Non-volatile memory cell and integrated circuit
TW200733366A (en) Split gate memory cell in a FinFET
TW200739923A (en) Vertical flash memory
AU2003279257A1 (en) Flash memory cell arrays having dual control gates per memory cell charge storage element
TW200518318A (en) Array of nonvolatile memory cells wherein each cell has two conductive floating gates
WO2008012464A3 (en) Eeprom charge retention circuit for time measurement
TWI257171B (en) Memory with charge storage locations
TW200802826A (en) Non-volatile memory devices having a vertical channel and methods of manufacturing such devices
TW200603171A (en) Flash memory with enhanced program and erase coupling and process of fabricating the same
WO2007133645A3 (en) Nand architecture memory devices and operation
TW200643952A (en) Bidirectional split gate nand flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
WO2008036552A3 (en) Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches
TW200603390A (en) Memory array including multiple-gate charge trapping non-volatile cells
TW200701236A (en) Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
WO2008102650A1 (en) Semiconductor storage device
JP2009503859A5 (en)
WO2007035284A3 (en) High performance flash memory device using a programming window for predetermination of bits to be programmed and dc-to-dc converter
AU2003265846A1 (en) Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation
WO2002037502A3 (en) Common source eeprom and flash memory
TW200515543A (en) NAND flash memory cell row and method of forming the same
WO2007056682A3 (en) Low voltage nanovolatile memory cell with electrically transparent control gate
ATE529892T1 (en) WRITE-PROTECTED MEMORY WITH EEPROM STRUCTURE
EP1814148A3 (en) Floating-gate memory cell with an auxiliary gate

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780034366.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07842450

Country of ref document: EP

Kind code of ref document: A2

REEP Request for entry into the european phase

Ref document number: 2007842450

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2007842450

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2009529310

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020097006107

Country of ref document: KR

ENP Entry into the national phase

Ref document number: 0905181

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20070911