JP4903873B2 - Nonvolatile memory cell array having floating gate formed from spacers in substrate trench and method for manufacturing the same - Google Patents

Description

  The present invention relates generally to non-volatile flash memory systems, and more particularly to a structure and process for forming a memory cell array utilizing substrate trenches to reduce the overall size of the array.

  There are a large number of commercially successful non-volatile memory products, especially those that are used today in the form of small form factor cards with flash EEPROM (electrically erasable and programmable read-only). Memory) cell array is used. Arrays having a NOR or NAND architecture are commonly used. One or more integrated circuit chips including a memory cell array are typically combined with a controller chip to form a complete memory system. Apart from the foregoing, some or all of the controller functions can be performed on the same chip including all or part of the memory cell array.

  In one type of NOR array, each memory cell has a “split channel” between the source and drain diffusions. A floating gate of the cell is arranged over one channel portion, and a word line (also called a control gate) is arranged over the floating gate and the other channel portion. This arrangement effectively forms a cell with two series transistors, one transistor (memory transistor) having a floating gate charge that controls the amount of current that can flow in the transistor portion of the channel. And the voltage of the word line, and the other transistor (select transistor) has a word line that functions as the gate of the transistor. The word line extends over the row of floating gates. Examples of such cells and their use in memory systems and methods for manufacturing such cells are described in US Pat. Nos. 5,070,032 (Patent Document 1), 5,095,344 (Patent Document 2), 5,315,541 (Patent Document 3), 5,343,063 (Patent Document 4), 5,661,053 (Patent Document 5), and 6,281,075 (Patent Document) 6).

  By changing the divided channel flash EEPROM cell, a steering gate disposed between the floating gate and the word line is added. The individual steering gates of an array extend over one column of floating gates perpendicular to the word lines. As a result, when reading or programming one selected cell, the burden on the word line that needs to execute two functions simultaneously is reduced. As these two functions, (1) there is a function as a gate of the selection transistor, therefore, an appropriate voltage for turning on / off the selection transistor is required, and (2) between the word line and the floating gate. There is a function of driving the voltage of the floating gate to a desired level via electric field (capacitive) coupling. It is often difficult to optimally perform both of these functions at a single voltage. With the addition of the steering gate, the added steering gate performs function (2), while the word line only needs to perform function (1). The use of steering gates in a single flash EEPROM array is described, for example, in US Pat. Nos. 5,313,421 and 6,222,762.

  One specific type of memory cell that efficiently utilizes the integrated circuit area includes two floating gates, each floating gate being binary (one bit per floating gate) or multiple programming states (floating 2 bits or more per gate). Two floating gates are disposed over the substrate channel between the source diffusion portion and the drain diffusion portion, and a selection transistor is disposed between the source diffusion portion and the drain diffusion portion. One steering gate is provided along each column of floating gates, and one word line is provided over the steering gate along each row of floating gates. When accessing a given floating gate for reading or programming, a steering gate over the other floating gate of the cell containing the floating gate of interest no matter what charge level is present in one floating gate Is raised until it is high enough to switch the channel on under the other floating gate. This operation effectively removes the other floating gate as a factor when reading or programming the floating gate of interest within the same memory cell. For example, the amount of current flowing through the cell that can be used to read the cell state is in this case a function of the amount of charge on the floating gate of interest, but the amount of charge on the other floating gate in the same cell. It is not a function.

  Thus, examples of arrays and operating techniques having dual floating gate memory cells are disclosed in US Pat. Nos. 5,712,180, 6,103,573, and 10,151. 248 (Patent Document 11). The dual floating gate memory cell array is usually formed on the entire surface of the semiconductor substrate. However, U.S. Pat. No. 6,151,248 further discloses a memory formed mainly in FIGS. 6 and 7 in the trench on the substrate surface along the surface area of the substrate adjacent to the trench. The cell is described. US Pat. No. 6,936,887 also describes a memory cell array partially formed in a substrate trench.

  In a NAND array, successive columns of three or more memory cells, such as 16 and 32, are connected to one or more select transistors between individual bit lines and a reference potential to form a cell column. A number of these columns extend word lines across cells in the row direction. During programming, the individual cells in the column are read and verified by strongly turning on the remaining cells in the column so that the current flowing in the column is the charge level stored in the addressed cell. Depends on. An example of an array of NAND architectures and their operation as part of a memory system is shown in US Pat. Nos. 5,570,315, 5,774,397, and 14,046. , 935 (patent document 15), 6,522,580 (patent document 16), 6,888,755 (patent document 17), and 6,925,007 (patent document 18). It is.

  There are various programming techniques for injecting electrons from the substrate onto the floating gate via the gate dielectric. The most commonly used programming mechanism is the book "Nonvolatile Semiconductor Memory Technology" edited by Brown and Brewer, IEEE Press, Section 1.2, pages 9-25 (1998) (a book edited by Brown and Brewer , "Nonvolatile Semiconductor Memory Technology," IEEE Press, section 1.2, page 9-25 (1998)) (Non-Patent Document 1). One technique, called “Fowler-Nordheim tunneling” (Section 1.2.1), provides a high electric field established by the voltage difference between the control gate and the substrate channel. Under influence, electrons are passed through a tunnel of floating gate dielectric. Another technique, commonly referred to as “thermoelectron injection” (Section 1.2.3), injects electrons from the cell channel into the floating gate region adjacent to the cell drain by channel thermionic injection in the drain region. Is done. Yet another technique, referred to as “source-side injection” (section 1.2.4), is that the substrate along the length of the memory cell channel so as to create conditions for electron injection from the drain into the channel region. The surface potential is controlled. Regarding source-side injection, Kamiya et al., “EPROM Cell with High Gate Injection Efficiency”, IEDM Technology Digest, 1982, pages 741-744 (Kamiya et al., “EPROM Cell with High Gate Injection Efficiency,” IEDM Technical Digest, 1982, pages 741-744) (Non-Patent Document 2) and US Pat. Nos. 4,622,656 (Patent Document 19) and 5,313,421 (Patent Document 7). Ogra et al., “Low Voltage, Low Current, High Speed Programmed Step-Division Gate Cell with Ballistic Direct Injection for EEPROM / Flash”, IEDM, 1998, 987-990 (Ogura et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM / Flash ", IEDM 1998, pages 987-990) (Non-Patent Document 3) In programming techniques, a high electric field is generated in a short channel and electrons are accelerated directly onto the charge storage element.

  One of two techniques for erasing a memory cell by removing charge from a floating gate charge storage element is mainly used in both of the two types of memory cell arrays described above. One technique erases the substrate by applying the proper voltage to the source, drain, substrate and other gates that tunnel through the dielectric layer between the floating gate and the substrate, causing electrons to tunnel. Is to do.

  Another erase technique is to move electrons from a floating gate to another gate through a tunnel dielectric layer disposed between the gates. In the first type of cell described above, a third gate is provided for that purpose. In the above-described second type cell, which already has three gates due to the use of the steering gate, the floating gate is erased according to the level of the word line without the need to add a fourth gate. This latter technique undoes and adds the second function performed by the word line, but since these functions are performed at different times, a compromise is made due to these two functions. The need will be avoided. Regardless of which erasing technique is used, a large number of memory cells are grouped together in a block of the minimum number of cells that are simultaneously erased in one “flash”. In one approach, each block contains enough memory cells to store some overhead data with 512 bytes of user data stored in one disk sector. Erasing many blocks at once, defect management, and other flash EEPROM system features are described in US Pat. No. 5,297,148. In another approach, each group contains enough cells to hold thousands of bytes of user data equal to data corresponding to 8, 16 or more host sectors that can be individually programmed and read. . An example of operating such a large block memory is described in US Pat. No. 6,968,421.

  Instead of electrically conductive floating gates, some flash memories utilize non-conductive dielectric materials that capture electrons. In either case, each individual memory cell includes one or more charge storage elements. Examples of the use of dielectrics are described in the aforementioned US Pat. No. 6,925,007 (Patent Document 18) and the documents referenced therein. In the case of a dielectric trapped charge memory cell, two or more charge storage elements can be formed as two or more regions of one continuous layer of spaced dielectric. One example of a suitable charge storage dielectric material is a three-layer oxide-nitride-oxide (ONO) composite material. Another example is one layer of silicon rich silicon dioxide material. As in almost all integrated circuit applications, there is pressure on the reduction of the silicon substrate area required to implement some integrated circuit function in the case of flash EEPROM systems. Increase the amount of digital data that can be stored in a given area of a silicon substrate, or increase the capacity and decrease the size, in order to increase the storage capacity of a given size memory card and other types of packages Both are constantly being sought. As another method of increasing the data storage density, there is a method of storing two or more bit data per memory cell. This method is accomplished by dividing the window of the memory cell threshold voltage range into three or more states. By using such four states, each charge storage element can store, for example, eight states in which 2-bit data and 3-bit data are stored per charge storage element. The structure and operation of a multi-state flash EEPROM is described by way of example in US Pat. Nos. 5,043,940 and 5,172,338.

US Pat. No. 5,070,032 US Pat. No. 5,095,344 US Pat. No. 5,315,541 US Pat. No. 5,343,063 US Pat. No. 5,661,053 US Pat. No. 6,281,075 US Pat. No. 5,313,421 US Pat. No. 6,222,762 US Pat. No. 5,712,180 US Pat. No. 6,103,573 US Pat. No. 6,151,248 US Pat. No. 6,936,887 US Pat. No. 5,570,315 US Pat. No. 5,774,397 US Pat. No. 6,046,935 US Pat. No. 6,522,580 US Pat. No. 6,888,755 US Pat. No. 6,925,007 U.S. Pat. No. 4,622,656 US Pat. No. 5,297,148 US Pat. No. 6,968,421 US Pat. No. 5,043,940 US Pat. No. 5,172,338 US Pat. No. 6,738,289 US Pat. No. 6,850,441

a book edited by Brown and Brewer, "Nonvolatile Semiconductor Memory Technology," IEEE Press, section 1.2, page 9-25 (1998) Kamiya et al., "EPROM Cell with High Gate Injection Efficiency," IEDM Technical Digest, 1982, pages 741-744 Ogura et al., "Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM / Flash", IEDM 1998, pages 987-990

  A floating gate charge storage device memory cell array is formed using trenches or cavities arranged along sidewalls with a floating gate having a gate dielectric between them without overlapping the substrate surface adjacent to the trench Is done. That is, the floating gate remains in the trench region in plan view. This is preferably done by utilizing spacers as floating gates, and isotropically depositing a layer of floating gate material, such as conductively doped polysilicon, on the array and in the trenches. All of the deposited floating gate material is anisotropically etched except for the spacers remaining along the trench sidewalls. At this time, a conductive control gate can be formed in the trench between the floating gate spacers and / or depending on the exact configuration desired for the memory cell, the select transistor is placed in the substrate surface area adjacent to the trench can do.

  The overall advantage of this structure is the efficient use of the substrate surface area. The majority of the memory cell channel length is placed vertically along the trench wall, thereby reducing the amount of substrate surface area required for each memory cell. The source and drain regions may be implanted at the bottom of the trench between the floating gates. This floating gate structure and the method of forming the floating gate may be used in a wide variety of types of flash memory arrays. If each such cell is used to form a NOR array of dual floating gate memory cells, for example, it is formed from two floating gates along the sidewalls of adjacent trenches, and a select transistor is formed within the substrate surface. And formed between the side walls. If a continuous column of memory cell transistors is used to form a NAND array, the connection diffusion is on the trench sidewall with the floating gate between the floating gates and along the substrate surface between adjacent trenches. Form along.

  One particular advantage of this positioning of the floating gate along the wall of the substrate trench is that in memory architectures, where appropriate, the floating gate can be programmed with ballistic implantation with increased efficiency. is there. That is, electrons were accelerated along the substrate channel length between the trenches and on the floating gate in a direct line path parallel to the substrate surface and sandwiched between the substrate trench sidewall and the floating gate and sidewall It can collide with the interface between the tunnel dielectric at a normal or near normal angle. Thus, there is no need to change the direction of electrons by the scattering mechanism, and scattering occurs while using the more common source side injection and thermionic injection program mechanisms. Enough to overcome the tunnel oxide barrier by not enveloping the floating gate from the trench and along the substrate surface, and by applying a voltage to the select gate slightly higher than the VT of the select gate Generates a high transverse electric field that accelerates the channel electrons to kinetic energy. Many of these thermionics affect the tunnel oxide without having to first scatter to change the direction of thermionic momentum. The high voltage across the floating gate can also facilitate acceleration of the electrons along the path to the floating gate when electrons traverse the channel region. The walls of the trench that forms the floating gate can be perpendicular to the substrate surface, which is ideal for efficient programming by ballistic implantation and allows the memory cell size to be minimized. But this is not a requirement. A substrate trench having vertical sidewalls is conveniently formed by anisotropically etching the substrate surface.

  Instead of forming a floating gate as the memory cell charge storage element, a dielectric charge trapping material may be substituted. For example, the same spacer technique can be used to deposit a central nitride layer of ONO. A constant thickness layer of oxide is formed on both sides of the nitride spacer, resulting in an ONO structure. Apart from the foregoing, silicon-rich silicon dioxide spacers can be formed in the same way as conductive floating gates, and dielectric layers provided on both sides of the floating gates are formed on such dielectric spacers. There is no need.

  Additional aspects, advantages, embodiments and features of the present invention are included in the following description of exemplary embodiments of the present invention and should be described in conjunction with the accompanying drawings.

  All patents, patent applications, papers, book portions, other publications, literature and things referred to herein are hereby incorporated by reference in their entirety for all purposes. . To the extent of any inconsistency or conflict in definition or use of terms between the incorporated publications, documents or things and this specification, those of this specification are valid.

1 illustrates in block diagram form a flash EEPROM system in which various aspects of the present invention may be implemented. 2 is a plan view of a partially configured dual floating gate memory cell array. FIG. FIG. 3 is a cross-sectional view of one embodiment of the structure of FIG. 2 taken along section AA. FIG. 3 is a cross-sectional view of one embodiment of the structure of FIG. 2 taken along section BB. 4 is an equivalent circuit diagram of a dual floating gate memory cell of the array of FIGS. 2, 3A, and 3B. FIG. FIG. 3 is a cross-sectional view of another embodiment of the structure of FIG. 2 taken along section AA. FIG. 6 is a cross-sectional view of the structure of FIG. 2 taken along section AA, showing a modification of the embodiment of FIG. FIG. 6 is a cross-sectional view of the structure of FIG. 2 taken along section AA, showing a modification of the embodiment of FIG. FIG. 6 is a cross-sectional view of another embodiment taken along a column of memory cells in a NAND array. FIG. 9 is an equivalent circuit of the NAND string of FIG. 8.

Memory System An example of a memory system embodying various aspects of the present invention is generally illustrated by the block diagram of FIG. Although a large number of individually addressable memory cells 11 are arranged in an array of equal rows and columns, other physical arrangements of cells are certainly possible. The bit lines shown to extend along the columns of the cell array 11 in this specification are electrically connected to the bit line decoder and driver circuit 13 via lines 15. In this description, the word lines shown to extend along the rows of the cell array 11 are electrically connected to the word line decoder and driver circuit 19 via the lines 17. The steering gate extends along the memory cell column of the array 11 and is electrically connected to the steering gate decoder and driver circuit 21 via a line 23. Each of decoders 13, 19, and 21 receives a memory cell address from memory controller 27 via bus 25. The decoder and the driver circuit are also connected to the controller 27 via the respective control signal lines and status signal lines 29, 31, and 33. The voltage applied to the steering gate and the bit line is adjusted via a bus 22 that connects the decoder and the driver circuits 13 and 21 to each other.

  The controller 27 can be connected to a host device (not shown) via a line 35. The host device may be a personal computer, a notebook computer, a digital camera, an audio player, and other various handheld electronic devices. The memory system of FIG. 1 is compliant with one of several current physical and electrical standards issued by PCMCIA, CompactFlash (registered trademark) association, MMC (registered trademark) association, SD group, etc. Generally implemented in the form of a card. When implemented in card format, line 35 terminates at a connector on the card that interfaces with a complementary connector on the host device. Many card electrical interfaces are compliant with the ATA standard, in which case the memory system appears to the host as if it were also a magnetic disk drive. There are other memory card interface standards. As an alternative to the card format, a memory system of the type shown in FIG. 1 is permanently embedded in the host device.

  When addressed via the bus 25, the decoder and driver circuits 13, 19, and 21 apply appropriate voltages to the respective lines of the array 11 according to the control signals of the respective control lines and status lines 29, 31, and 33. Generate and execute the programming function, read function and erase function. Any status signal, including voltage levels and other array parameters, is output by the array 11 to the controller 27 via the same control and status lines 29, 31, 33. A plurality of sense amplifiers in circuit 13 receive a current level or voltage level indicative of the state of the memory cell addressed in array 11 and provides information about these states to controller 27 via line 41 during a read operation. provide. A large number of sense amplifiers are usually used to allow the state of a large number of memory cells to be read simultaneously. During a read operation and a program operation, a row of cells is typically addressed at a time through circuit 19 to access a plurality of cells in the addressed row selected by circuits 13,21. In general, all cells in many rows are addressed together as a block so that they are simultaneously erased during an erase operation.

  Bit line decoder and driver circuit 13 is connected to a global bit line via line 15, and the global bit line is selectively connected to a source region and a drain region of the array. The source and drain of the column of individual memory cells are connected to an appropriate programming voltage for reading or programming depending on the address supplied via bus 25 and the control signal supplied via line 19.

  Steering line decoder and driver circuit 21 is connected to the steering gate via line 23 to individually select the steering line, address provided on bus 25, control signal on line 33, and data from driver and sense amplifier 13 Accordingly, the voltage of the steering line can be controlled.

  The selection gate decoder and driver circuit 19 are connected to a word line in order to individually select one row of cell arrays. At that time, each cell in the selected row can be read or written by the bit line, the steering gate decoder, and the driver circuits 13 and 21.

  The operation of the memory system as shown in FIG. 1 is described in the patents identified in the background section above and other patents assigned to SanDisk Corporation, the assignee of the present application. In addition, US Pat. No. 6,738,289 describes an exemplary data programming method.

Exemplary Embodiment of Dual Floating Gate Memory Cell Array An exemplary NOR memory array structure formed on a single integrated circuit chip having a floating gate formed by spacer technology is shown in FIGS. The equivalent circuit of the resulting memory cell is shown in FIG. Referring mainly to the plan view of FIG. 2, a two-dimensional array of trenches 51-66 preferably etches long parallel trenches first and then defines shortened trenches 51-66 within the trenches. Thus, a surface 49 of the semiconductor substrate 50 is formed. These trenches consist of two sets of electrically conductive control gate lines, word lines 69-72 having a length extending in the x direction, and a steering gate having a length extending in the orthogonally oriented y direction. Crossed by lines 75-78. Optionally, but preferably, the array of conductive shields 81-92 is recessed in the surface 49 of the substrate 50 between adjacent ones of the trenches 51-66 in the y direction. Each shield is electrically connected to one of the steering lines 75-78 that passes through the shield. These conductive shields and surrounding dielectrics are periodically placed along the initially formed elongated trench to form a defined length of trenches 51-66 in which the floating gate is located.

FIG. 6 is a cutaway view of FIG. 2 along cross-sections AA and BB, shown in FIGS. 3A and 3B, respectively, with the components formed in trenches 51-66 being shown in FIGS. Each trench 51-66 includes a memory cell floating gate, a select gate, and a dielectric layer. Taking trench 61 as a representative, dielectric material layer 101 covers the walls and bottom of the trench. Layer 101 is preferably made of silicon dioxide (eg, SiO ₂ ). Two conductive floating gates 103, 105 are formed as spacers along opposite sidewalls of the trench in the x direction. Sufficient space is left in the x direction between the floating gate for the dielectric layer 107 and the steering gate 109 filling this space. Dielectric layer 107 is preferably composed of two layers of silicon dioxide on opposite sides of a layer of silicon nitride (eg, Si ₃ N ₄ ) in a structure commonly referred to as “ONO”. It should be noted that the ONO layer is confined in the region between the floating gate and the steering gate, avoiding the channel region. This improves the durability of the memory cell, reduces noise and prevents phenomena that can be caused by trapped charges in the nitride layer over time.

  Gates 103, 105, and 109, dielectric layer 101 along the sidewall, and intermediate dielectric layer 107 all fill trench 61 in the x direction. The buried N + diffusion 110 extends in the y direction and is located under the trenches 53, 57, 61, 65 to provide the source and drain regions that are part of the memory cell. The remaining trenches contain the same structure and form. As specific for use below, adjacent trenches 60 include floating gates 111, 113, steering gates 115, and a dielectric layer arranged similarly to trench 61. The buried diffusion portion 117 exists under the trench 60 and other trenches in the same column.

  The floating gate is formed by depositing polysilicon material over the entire memory cell array that is to be included in the trench, and then anisotropically etching the layer until a spacer such as the floating gate spacer 103, 105 remains in the trench. It is preferable to form by doing. A chemical mechanical polishing (CMP) step may be performed to remove any portion of the floating gate spacer material that may remain on the substrate surface 49. In this embodiment, the resulting floating gate is located entirely within each trench under the substrate surface 49. Steering gates 109 and 115 are also conveniently located generally under the substrate surface 49 and in the trenches of the steering gates.

  A conductive control gate line is disposed on the substrate surface 49 across the trench. Steering gate lines 75-78 extend across the trench in the y direction and contact the steering gate of the trench and the conductive shield between the trenches. Line 77, for example, contacts intermediate conductive shields 83, 87, 91 and extends across and electrically contacts steering gate 109 and the other steering gates in the row. A dielectric insulating layer (not shown) is disposed between the steering gate lines and any portion of the substrate surface 49 that they traverse. The dielectric material surrounds the steering gate line. The line 77 includes, for example, two dielectric layers 121 and 123. The dielectric layers 121 and 123 are disposed on the upper surface of the line 77 and have the same extension as the surface thereof. The layer 121 is preferably made of silicon dioxide, and the layer 123 is preferably made of silicon nitride. The spacers 125 and 127 are formed along the side walls in the x direction of the conductive lines 77 and the dielectric strips 121 and 123 on the conductive lines 77.

  The word lines 69 to 72 are arranged perpendicular to the steering gate line over the steering gate line surrounded by the dielectric. Due to the thickness of the intermediate dielectric, there is little or no coupling between the word line and the steering gate line. In addition, the word lines are separated from the substrate surface between the trenches in the x direction by a layer 129 of gate dielectric, preferably silicon dioxide. The area of the word line adjacent to the gate dielectric 129 forms the select gate of the memory cell. The channel region of the select transistor is present in the substrate surface 49 on the opposite side of the gate dielectric layer 129 between the trenches.

  The shield is a dielectric such as layers 131, 132 along the side wall of the shield 91 separating it from the edge of the floating gate on one side in the y direction, and a layer 133 between the bottom surface of the shield 91 and the substrate surface 49. Surrounded by the body. The bottom layer 133 is relatively thick to minimize the coupling between the shield 91 and the substrate surface 49. On the other hand, the side layers 131, 132 are relatively thin to maximize the coupling between the shield 91 and the edge of the floating gate on one side of the shield. Since the shield 91 is electrically connected to the steering gate line 77, this provides an area with increased coupling between each steering gate and a floating gate in the same column as the steering gate. Memory cells with increased coupling ratio couple a larger percentage of the voltage across the steering gate to the capacitively coupled floating gate. At the same time, because of the thin floating gate in the x direction, as can be seen from FIG. 3A, the coupling between the floating gate and the buried bit line diffusion can be kept small.

  One exemplary configuration for the arrays of FIGS. 2, 3A, and 3B includes continuous trenches formed in the substrate in both the x and y directions that intersect each other. The floating gate and the steering gate are arranged in a trench extending in the y direction between the trenches in the x direction. The shield element is disposed in a trench extending in the x direction where the shield element intersects the trench in the y direction. At this time, a suitable field dielectric material fills the trench in the x direction between the shield elements.

  The example structure of FIGS. 2, 3A, and 3B utilizes doped polysilicon or other suitable conductor material formed from five individual deposits of material at different points in the process. In the process embodiment described below, the floating gate is formed from a first deposit of conductive material, the steering gate is formed from a second deposit, and the shield element is formed from a third deposit. The steering gate line is formed from the fourth deposit, and the word line is formed from the fifth deposit. The polysilicon may be doped during film formation, or may be formed without doping, and then ion-implanted after film formation, as described above. The last layer of polysilicon in which the word line is formed may be silicided to reduce the resulting word line resistance, or for this purpose, has a metal bonded to its top surface. May be. Apart from the above, the word line may be entirely made of metal as the fifth layer.

  FIG. 4 is an equivalent circuit of one memory cell of FIGS. 3A and 3B, and the same reference numerals are used with a prime symbol ('). Three transistors are connected in series with the buried bit line diffusion portions 110 ′ and 117 ′. The left storage transistor includes a floating gate 113 ', and the right storage transistor includes a floating gate 103'. Among these storage transistors, the selection transistor has a control gate 71 '. The memory cell array shown in the present specification may be processed in substantially the same manner as the dual floating gate memory cell array of the aforementioned US Pat. No. 6,151,248.

  As shown in FIG. 3A, the substrate channel of this one memory cell is divided into three segments. One segment (T 1 -left) is along the vertical sidewall of the trench 60 adjacent to the floating gate 113 between the diffusion 117 and the substrate surface 49. This is part of the storage transistor on the left side of the memory cell described. The adjacent segment (T2) is along the substrate surface 49 between the walls of adjacent trenches 60,61. The third segment (T 1 -right) is along the vertical sidewall of the trench 61. As long as processing is possible, the trenches may be formed as small in the x and y dimensions across the substrate surface. As a result, a very compact memory cell array can be obtained in the x direction over the substrate surface. Thus, the amount of integrated circuit area per memory cell is very small. Assuming the same processing scale, the density of memory cells can be double that when floating gates are placed across the substrate surface. At the same time, the select gate channel length (T1 distance) may increase slightly and the floating gate channel length (T1) may increase significantly.

  A preferred programming mechanism for the memory cells shown in FIGS. 3A and 3B is ballistic programming. That is, electrons are accelerated in the T2 region of the channel in a direction substantially parallel to the substrate surface 49 by a suitable voltage applied to the word line, select gate line, buried bit line diffusion and substrate. The fast electron path hits one of the floating gates 103 or 113 substantially perpendicular to its wide plane, depending on which floating gate is being programmed. Programming efficiency can be orders of magnitude higher than standard source side injection. Part of the floating gate preferably does not overlap the substrate surface 49 in the T2 region, thereby freeing up a field effect T2 region that may interfere with this direct high energy electron path. The sidewalls of the trench as shown in FIG. 3A are preferably vertical (perpendicular to the substrate surface 49), as shown for the most efficient ballistic programming, but for other reasons, as described above. If it is more convenient, it may be slightly inclined.

  There are several possibilities for removing charge from the floating gate to erase the memory cell, three of which are described herein. One is to pass electrons through the select gate dielectric 129 from the relatively sharp tip of the floating gate to the adjacent word line 71. A high erase voltage is applied to the word line for this purpose. Apart from that described above, the floating gate may be erased to its vertical channel portion via a floating dielectric layer along the vertical plane of the trench. In this regard, a voltage in the range of 0--0.5V is applied to the bit line (apart from that described above, the bit line can float to prevent the possibility of erasing the bit line. 0V is applied to the substrate and within -20V is applied on the steering gate. Another possibility is to erase between the bottom of the floating gate and the buried diffusion bit line below the bottom of the trench via the floating gate dielectric layer at the bottom of the trench. Exemplary voltages include 5V applied to the bit line, 0V applied to the substrate, and -15V applied to the steering gate. This last option has the advantage of not erasing through the floating gate or select gate dielectric layers, thus avoiding trapped charges in these layers over time from many erase operations that typically affect programming and reading To do.

It should be noted that the memory cell array of FIGS. 2, 3A and 3B provides shielding between adjacent floating gates in both the x and y directions. Since the steering gate extends between the floating gates to the bottom of the trench in the same trench, the steering gate provides a shield in the x direction. In the y direction, shield elements 81-92 provide such insulation. Field binding on one of the floating gate for the adjacent floating gate is can be a source of the read error, thereby significantly reduced.

Process for Producing Dual Floating Gate Memory Cell Array One set of process steps (manufacturing method) for producing the memory cell array of FIGS. 2, 3A and 3B will be described below. The initial step is to implant ions such as boron from the surface where the array is formed into the blank substrate. Different implants with different energies and doses allow control of the doping level along the resulting vertical channel portion T1. The vertical orientation of the floating gate portion of the channel allows such selective doping along the channel length to be done with relative ease and reliability. For example, it may be desirable to provide the highest ion concentration at a depth that coincides with the midpoint along the floating gate channel length T1. This is because the threshold voltage V _T is highest at the midpoint as compared to any other point along the channel length T1, and more by the floating gate rather than by the buried bit line diffusion or select gate. Forms a strongly controlled bottleneck point. Placing the bottleneck point at the middle point of T1 to the extent that the bottleneck point defines the behavior of the memory cell means that the bottleneck point is connected to the upper region where ballistic electron injection occurs and the buried bit line diffusion unit. The penetration of is away from both the lower region that may be selected for erasure.

  Negative ion gradients with increasing depth may be introduced near the substrate surface, which is advantageous for improved production of thermionics used during programming. Furthermore, control of the doping level at the corner of the channel where a gap exists between the select gate and the floating gate results in the gap not determining the behavior of the memory cell.

  After implantation, a thin silicon oxide layer is grown over the area of the substrate surface where the array is formed. This serves as a buffer for the next layer of silicon nitride deposited on the oxide layer. The nitride layer is then masked, preferably a length extending in the y direction with minimal width and spacing between the strips in the x direction as much as possible using lithography and other aspects of the specific process. Etch into a pattern of strips having. The substrate surface between the nitride strips and the region of the thin oxide layer is then anisotropically etched with the nitride strips acting as a mask. A trench having substantially vertical walls is formed in the substrate by this etching step to a depth slightly greater than the desired floating gate vertical channel length T1. Each column of trenches 51-66 (FIG. 2) is finally formed in one of these trenches.

  A thick layer of oxide is then deposited isotropically over the nitride strip and over the entire area of the array in the trench. This oxide layer is then anisotropically etched, leaving oxide spacers along the common sidewalls and nitride strips of the trench. The deposited oxide layer and etch thickness are selected to leave a narrow space between the spacers in the x direction. These spacers and nitride strips are used as implantation masks. Buried N + implants using various energies such as arsenic are made at the bottom of the trench through this mask between the spacers. In this manner, the bit line diffusion portion is formed as a strip extending along the bottom of the trench in the y direction. The implanted ions are later diffused outward in the x direction as a result of further processing steps at high temperatures, forming the bit line diffusions 110, 117, etc. shown in FIGS. 3A and 3B.

  The oxide spacers, nitride strips and the underlying oxide are then all etched. An oxide layer is then grown over the entire memory array region to a thickness of 8 nm to 10 nm and conformed to the stepped contour of the substrate surface. This portion of the layer in the trench eventually becomes the oxide layer 101 of FIGS. 3A and 3B. A first polysilicon layer (Poly1) is then isotropically deposited over the array region with a thickness of 10 nm to 20 nm. The layer is then anisotropically etched back, leaving a spacer strip extending continuously along the trench sidewall in the y direction and spaced in the x direction within the trench. Later, some of these polysilicon strip lengths are removed, leaving the spacer floating gates of the array.

  An ONO layer is formed over the array region, and a portion over the polysilicon spacer strip that remains as a floating gate forms the interpoly dielectric layer 107 of FIGS. 3A and 3B. To form the ONO layer, a 5-6 nm thick oxide layer is first deposited and / or grown. Next, a 5 to 7 nm nitride layer is formed on the oxide layer. A final 5-6 nm thick oxide layer is then grown or deposited on the nitride layer, or both. The high temperature oxide densification step may be performed after each oxide layer is formed. Apart from the above, the subsequent high temperature annealing step also performs a densification task, so this may be omitted if a high temperature annealing step is included in the process.

  A second layer of polysilicon (Poly2) is isotropically deposited over the array region to a thickness sufficient to completely fill the trench between the Poly1 ONO coated strips. A CMP step is then performed to remove all material down to the substrate surface. This leaves a Poly2 strip extending in the y-direction, which when separated then forms the steering gates 109, 115, etc. of FIGS. 3A, 3B.

  The next few steps form a nitride mask and use it to etch the Poly1 and Poly2 strips, the dielectric layer surrounds them, and the substrate in the strip extends in the x direction Have a length. The resulting x-direction trench depth is preferably the same as the previous floating gate trench etch. Non-selective etching is preferable so that each of Poly 1 and Poly 2 is etched at approximately the same rate in the oxide layer, ONO layer, and silicon substrate. It is in these trenches that shield elements 51-66 (FIG. 2) will be formed later. This etch separates the Poly1 and Poly2 strips as shown in FIGS. 3A and 3B. Since the resulting steering gates are isolated from each other in the y direction, steering gate lines 75-78 (FIGS. 2, 3A, 3B) are formed later and the lines are connected together in a column.

  Next, a dielectric layer is formed on the array region by growing an oxide layer and forming an isotropic oxide film, etc., and the dielectric layer 131 having an unequal thickness in the trench in the x direction, 132, 133 (FIG. 3B). A third layer of polysilicon (Poly3) is then deposited over the oxide in the x-direction trench. The region is then exposed to CMP again to remove polysilicon and oxide down to the substrate surface. The residue is an oxide that separates the Poly3 strip from the walls of the substrate trench and the walls of the substrate trench, extending in the x direction, and within the trench in the x direction as a whole. These Poly3 strips are later separated, leaving shields 81-92.

  Certainly, this separation is performed in the next series of steps. As in the plan view of FIG. 2, the resulting shield length in the x-direction is preferably greater than the width of adjacent trenches 51-66, but the shield length is different from that described above. It is also possible to have the same size. Doing so means that Poly3 strip segments that are smaller than the line width of the process used need to be removed. Therefore, first, an etching mask is formed on the array region having openings according to the line width of the process arranged on the region of the Poly3 strip to be removed. Spacers are then formed in the y direction along at least the edges of these openings to narrow the openings. The portion of the Poly3 strip that is exposed through these limited openings is removed by an anisotropic etch step, thereby leaving individual shields 81-92.

  The next series of steps forms steering gate lines 75-78. A fourth layer of polysilicon (Poly4) is deposited over the area of the array. Next, an etching mask is formed on the Poly4 layer in the form of strips extending in the y direction, covering part of the layer that remains and becomes lines 75-78. Since this mask cannot be aligned with other pre-formed elements, it is desirable to make the width of the remaining Poly4 strip narrower than the line width of the process. Some misalignment in the x direction can then be tolerated.

  These narrow mask openings are obtained by first forming an oxide mask on the Poly4 layer in the x direction equal to the minimum line width of the process used, with the strip having a width and a space between the strips. May be. An oxide material spacer is then formed along the edge of the opening to narrow the opening. A nitride layer is then deposited on the oxide material and on the Poly4 layer through the narrowed openings between the oxide spacers. The structure is then subjected to CMP down to the oxide material, thereby leaving a nitride strip extending in the y direction at the desired steering gate line width. The oxide material between the nitride strips is removed by selective etching. The Poly4 layer is then anisotropically etched through the resulting nitride mask to remove material from the Poly4 layer other than where the nitride strip is present. As a result, steering gate lines 75 to 78 are obtained.

  As shown in FIGS. 3A and 3B, the nitride mask strip is preferably left in place on the Poly4 strip. An oxide spacer is then formed along the sides of the stack of Poly4 and nitride strips to provide sufficient insulation between the Poly4 strip (steering gate line) and the word line formed on the Poly4 strip. To do. The added height to the stack provided by the nitride layer results in spacers (such as 125, 127 in FIG. 3A) and Poly4 strip regions (such as steering gate line 77 in FIG. 3A) reach a sufficient thickness.

  Next, an oxide layer is grown and / or deposited to form a select gate dielectric layer 129 (FIG. 3A) on the exposed surface of the substrate. Next, a fifth layer of polysilicon (Poly5) is formed on the array region in which the word lines 69 to 72 are formed. The Poly5 layer may be separated into word lines that are narrower than the minimum line width of the process used in the same manner as described above to form narrow steering gate lines 75-78 from the Poly4 layer. This mask is, of course, placed with its strip extending in the x direction. This process of reducing the width of the resulting polysilicon strip allows some misalignment of the resulting Poly5 line in the y direction.

  Further steps (not shown) include a first set of metal lines separated by dielectric layers periodically connected along their length to polysilicon steering gate lines 75-78, and standard processing techniques. Forming a second set of metal lines connected along the length of the word lines 69-72.

Other Embodiments of Dual Floating Gate Memory Cell Array There are many variations that can be made to the architecture and process described above, retaining their advantages and providing other advantages. One variation is to create a trench in the shallower substrate shown in FIGS. 3A and 3B and then float from the trench at a distance on the substrate surface and any control gate dielectric material formed on the substrate surface. And extending the steering gate structure. Such a memory cell array is shown in FIG. 5, which is a cross-sectional view corresponding to FIG. 3A for the embodiment described above. Elements of the same or substantially the same structure shown in FIG. 5 are identified by the same reference numerals as in FIG. 3A, and different elements having the same reference numerals as the corresponding parts of the elements are double prime symbols (“) Is added.

  The main advantage of the embodiment of FIG. 5 is that the substrate channel portion T1 facing the floating gate of the memory cell without reducing the coupling region between the floating gate and the steering gate if the gate remains the same size. -The left and T1-right lengths are reduced. This is because the capacitive coupling amount between each floating gate and the substrate is in the denominator of the ratio, and the coupling level between the floating gate and the steering gate is in the numerator, so that the floating gate of the cell is the coupling ratio of the steering gate. Desirably increase. The select transistor channel length T2 need not be affected.

  Another advantage of the structure of FIG. 5 is that the overlap increases between each floating gate and the word line. More area of the floating gate 113 is located, for example, opposite the word line 71 ". This depends on the nature and thickness of the dielectric between the floating gate and the word line. This makes it possible to use the word line to apply a voltage to the floating gate during erasure to the buried bit line diffusion or substrate channel, thereby erasing Use word lines to help control the floating gate voltage during programming, such as by providing the minimum floating gate voltage required to start floating gate programming in a row of word lines May be.

  In addition, as the coupling between the word lines and the floating gates in the word line rows increases, the alternating current is applied while the word lines perform read and verify operations in the word line rows to reduce noise. It can be driven by the (AC) signal. This technique is described in US Pat. No. 6,850,441.

  Similar to the embodiment of FIGS. 3A and 3B, from FIG. 5, a steering gate line, such as line 76, is located on either side of the trench 60 (60 ″ in FIG. 5) that includes the steering gate 115. It should be noted that the lines extend across the array in the y direction in electrical contact with the intersecting steering gate and intermediate shield elements, such as shield elements 86, 90 (FIG. 2). The element is formed with the upper surface at or below the substrate surface 49 (see FIG. 3B), and when the gate structure in FIG. 5 is raised, the steering gate line 76 and the like are mounted on the steering gate 115 and the like. Then, it is lowered to both sides of the steering gate in the y direction, and comes into electrical contact with the shield element 90 and the like.

  The modified array of FIG. 5 may be made in one variation by the process described above for the arrays of FIGS. 2, 3A, and 3B. When the first polysilicon layer (Poly 1) is formed because the floating gate and the steering gate extend on the substrate surface, the nitride mask formed in the initial step is left in place on the substrate surface. This nitride mask is used to etch the trench in the silicon surface, and in this variant, the trench is not as deep as before. The nitride mask strip extends in the y direction and covers the select gate region of the memory cell, and its thickness is equal to the dimension h, the desired distance between the top of the floating / steer gate structure and the substrate surface 49. It is controlled to become. Poly 1 is then deposited on the nitride mask strip and in the vertical extension of the substrate trench formed by the substrate trench and nitride strip. The floating gate spacer resulting from the anisotropic etching of the Poly1 layer extends on the nitride strip on the substrate surface by a distance h. The nitride mask strip is later removed.

  Since the nitride mask strip remains after the floating gate spacer is formed, the buried bit line diffusion may then be implanted using the nitride strip and floating gate as an implantation mask. Since the floating gate narrows the width of the trench into which ions are implanted, the oxide spacer formed in the above description of the process of FIGS. 3A and 3B before the Poly 1 is deposited is not necessary. The additional steps necessary to form and remove those oxide spacers can then be omitted.

  If it is desired to increase the steering-floating gate coupling ratio but keep the word line (select gate) -floating gate coupling ratio low, the word line and its select gate structure shown in FIG. 5 may be modified. Three different examples of select gate structures that reduce the coupling region with floating gates are shown in FIGS. 6 and 7, wherein the same or substantially the same elements as shown in FIG. 5 are identified by the same reference numerals. The It is not necessary to reduce the select gate channel length T2 while reducing the coupling with the floating gate.

  Referring first to FIG. 6, select gates such as gates 135 and 137 are individually formed from a conductive material such as doped polysilicon. These select gates are then connected together by horizontal word line conductors 139 extending in the x direction along the row of memory cells and conductors 141, 143 extending in contact with the individual select gates. Since a thin selection gate can be formed, the coupling region with the floating gate along the vertical edge of the selection gate can be reduced. While the horizontal portion 139 is made of metal, the vertical portions 141, 143 and the like can also be made of doped polysilicon. Apart from the above, all of the word line portions 139, 141, 143, etc. can be made of metal.

  FIG. 7 shows a further modification in which thin select gates 147, 149 are formed, and then, as shown in FIG. 6, second layers 151, 153 having a triangular shape in this cross section are formed separately. The triangular portion is placed with the surface adjacent to the upper narrow edge of the floating gate and with a thin layer of dielectric between them, which facilitates erasure of the floating gate relative to the select gate. However, at the same time, the coupling between the select gate and the floating gate is minimized. The individual select gate structures are then connected by a conductive word line, such as word line 155, which is preferably a metal that includes a downwardly descending portion in contact with the select gate structure.

  Although the embodiments of FIGS. 2-7 are described as specific examples to utilize dual gate memory cells connected in a NOR architecture, the described trench gate structure is utilized in other memory cell array configurations. It is understood that it may be.

Embodiments of NAND Memory Cell Array The use of the spacer technique described above for forming a floating gate in a trench can also be used to form a memory cell array having a NAND architecture. One NAND embodiment is shown in cross section through the NAND string portion of the memory cells connected in series in FIG. A series of trenches 163, 165, 167, 169 are formed in the surface 159 of the semiconductor substrate 161. After the dielectric layer is formed on the sidewalls and bottom of the trench, two floating gates are formed in each trench of the doped polysilicon material spacer (from Poly 1) as described above. Eight such floating gates 171 to 178 are included in the explanatory diagram of FIG. After the formation of the spacer floating gate, source diffusion portions and drain diffusion portions 181 to 189 are formed by ion implantation. Apart from the above, ion implantation may be performed after the trench is formed, although it is before the floating gate is formed.

  After forming a dielectric layer on the exposed surfaces of floating gates 171-178 and on substrate surface 159 between the trenches, a word line control gate is formed extending across the array in a direction perpendicular to the memory cell columns. To do. Indeed, the array is made up of many such columns in parallel columns, with word lines extending across the columns along the rows of memory cells. Since there is a separate word line intersecting each floating gate, it is necessary to form two such word lines in each trench 163, 165, 167, 169 rather than the single steering gate of the previously described embodiment.

  Thus, the word line is formed from two layers of polysilicon that are sequentially deposited and etched. A first word line layer of polysilicon (Poly2) covers the entire array extending into the trench between the floating gates. The mask formed over the Poly2 layer allows removal of the mask with a pattern that leaves the first set of word lines 191-194, all other word lines along the memory cell column. After covering the exposed surfaces of these word lines with a dielectric, a layer next to polysilicon (Poly3) is deposited over the array, including the remaining space in the trench. The Poly3 layer is then covered and etched to leave a second set of word lines 197-201, which are the remaining word lines of the array. The word line is not self-aligned with the other components of the column, and each trench includes 4 layers of polysilicon and 5 layers of dielectric, so the size of the trench along the column is In some cases, it needs to be larger than the smallest resolving element of the process used.

  The electric equivalent circuit of the NAND memory cell column in FIG. 8 is given as FIG. 9, and the corresponding reference numbers with the prime symbol (') added are given to the corresponding elements. At the end of each column is typically a switching transistor 205, 207 for selectively connecting the column to a reference potential such as its global bit line and ground.

CONCLUSION While various aspects of the present invention have been described in connection with exemplary embodiments thereof, it is understood that the invention is entitled to protection within the full scope of the appended claims. Let's be done.

Claims (31)

A non-volatile memory formed on a semiconductor material,
A rectangular array of trenches extending to the top surface of the semiconductor material along a first direction and a second direction that are perpendicular to each other over the top surface, wherein the individual trenches are spaced apart in the first direction; and A first opposing wall extending at a bottom direction that is coupled to a bottom of the trench by a bottom surface that extends in a second direction, is perpendicular to the top surface, and is parallel to the top surface; and is spaced apart in the second direction; A rectangular array of trenches including a second opposing wall extending between the top surface in a first direction;
Forms spacers along the first opposing walls of the individual trenches with spaces in the first direction without extending beyond the trenches in the first direction beyond the first opposing walls A pair of charge storage elements comprising polysilicon ,
Disposed in the trench between the charge storage elements in a first direction and individually separated from at least one of the charge storage elements in the trench by a dielectric, At least a first conductive control gate connected to a first conductive control line extending in a direction;
At least the bottom surface of each trench between the pair of charge storage elements in a first direction, a source region and a drain region disposed within the semiconductor material, the source and drain regions of said trench, first as a bit line A source region and a drain region connected together along the direction of 2;
A non-volatile memory comprising: The non-volatile memory according to claim 1.
A non-volatile memory further comprising a second conductive control gate disposed in a first direction over a region of an upper surface between the trenches and connected to a second control line extending in the first direction. The non-volatile memory according to claim 2.
The second control gate is electrically coupled to a semiconductor material in the region over the upper surface to form a select transistor between the trenches in the first direction. The non-volatile memory according to claim 1.
The first control gate is field-coupled to one of the charge storage elements in each trench, but not to other charge storage elements, and the non-volatile memory is connected to the other in the trench. Are arranged in the trench between the charge storage elements in the first direction and extend in the second direction so as not to be coupled to one of the charge storage elements. A non-volatile memory further comprising a second conductive control gate connected to the second conductive control line. The non-volatile memory according to claim 2.
The charge storage element is a non-volatile memory that extends from the trench on the upper surface so as to be electrically coupled to the second control gate. The non-volatile memory according to claim 5.
The second control gate is also electrically coupled to the semiconductor material in the region on the top surface to form a select transistor between the trenches in the first direction, and the second control line extends in the first direction. Non-volatile memory. The non-volatile memory according to claim 1.
A non-volatile memory further comprising a shield disposed in the semiconductor material between adjacent trenches in a second direction and electrically connected to a first control line disposed over the substrate. A non-volatile memory formed on a semiconductor material,
A rectangular array of trenches extending over the top surface to the surface of the semiconductor material along a first direction and a second direction that are perpendicular to each other, wherein the individual trenches are spaced apart in the first direction; and A planar first opposing wall extending in the second direction and joined at the bottom by a flat bottom surface, further spaced apart in the second direction and between the bottom surface and the top surface A rectangular array of trenches including a second opposing wall extending in a direction;
Along the first opposing walls, disposed in the individual trenches with a first layer of dielectric therebetween, and having a first opposing wall in a first direction. Two floating gates that are arranged without extending beyond the outside of the trench and are formed as spacers from conductively doped polysilicon;
A control gate disposed in each trench, in a first direction, between two floating gates, with a second layer of dielectric in between;
A first set of conductive lines connected to the control gate and extending in a second direction and having a length along the second direction;
Source and drain regions located in the semiconductor material at the bottom of the individual trenches;
In a first direction, between adjacent trenches, disposed over the top surface with a third layer of dielectric therebetween, and the top surface of the semiconductor material through the third layer of dielectric A select gate that is field coupled with
A second set of conductive lines connected to the select gate and extending in a first direction and having a length along the first direction;
Thereby, each memory cell has a channel region extending in the semiconductor material between the source and drain regions of the trenches adjacent in the first direction. The non-volatile memory according to claim 8.
The floating gate and the control gate are non-volatile memories included in a trench having the same extension as the upper surface. The non-volatile memory according to claim 8.
The floating gate and the control gate are nonvolatile memories extending from the trench on the upper surface at a sufficient distance for the electric field coupling of the floating gate with the selection gate. The non-volatile memory according to claim 10.
The floating gate is a non-volatile memory extending a distance on the selection gate from the trench. The non-volatile memory according to claim 8.
With a fourth layer of dielectric between them and electrically connected to the conductive shield, the same extension depth as the array of trenches, between the trenches in the second direction and within the semiconductor A non-volatile memory further comprising a conductive shield disposed on the substrate, thereby providing electrostatic shielding between the floating gates in a second direction. The non-volatile memory according to claim 12,
A non-volatile memory, wherein the electrical connection with the conductive shield includes a first set of conductive lines extending across and in contact with the conductive shield. The non-volatile memory according to claim 8.
The trench comprises a continuous channel in a semiconductor material extending in a second direction and having a length spaced in the first direction, and an insulating dielectric disposed between the trenches A non-volatile memory formed in a continuous channel along its length. The non-volatile memory according to claim 11.
The non-volatile memory, wherein the select gate is an integral part of a second set of conductive lines extending generally along the distance that the floating gate extends over the top surface. The non-volatile memory according to claim 11.
The select gate has a thickness that is significantly smaller than the distance that the floating gate extends over the top surface, and is connected to the second set of conductive lines by a conductor that extends the distance that the floating gate extends over the top surface. Non-volatile memory. The non-volatile memory according to claim 16.
The conductor between the select gate and the second set of conductive lines is formed with the surface disposed opposite the upper end of the floating gate extending over the top surface, the surface comprising the top surface and Non-volatile memory that forms an acute angle. A non-volatile memory formed on a semiconductor material,
A rectangular array of trenches extending to the top surface of the semiconductor material along a first direction and a second direction that are perpendicular to each other over the top surface, wherein the individual trenches are spaced apart in the first direction; and A planar first opposing wall extending in the second direction and joined at the bottom by a flat bottom surface, further spaced apart in the second direction and between the bottom surface and the top surface A rectangular array of trenches including a second opposing wall extending in a direction;
2 located in individual trenches along the first opposing walls without extending beyond the first opposing walls in the first direction in the first direction and in the form of spacers. A charge storage device comprising two polysilicons ;
A first control gate and a second control gate disposed in each trench between two charge storage elements in a first direction, said first control gate being a charge in each trench; A first control gate and a second control gate that are field coupled to one of the storage elements, and wherein the second control gate is field coupled to another one of the charge storage elements in the trench;
A first set of conductive lines connected to the first control gate and extending in a second direction and having a length along the second direction;
A second set of conductive lines connected to the second control gate and extending in the second direction and having a length along the second direction;
Source and drain regions disposed along the top surface between the trenches in a first direction in the semiconductor material at the bottom of the individual trenches;
A non-volatile memory comprising: The nonvolatile memory according to claim 1 or 18,
The non-volatile memory in which the charge storage element is disposed entirely in the upper surface or in the trench below the upper surface. The non-volatile memory according to claim 18,
A plurality of columns of memory cells connected in series are arranged in a first direction across a plurality of trenches, a first termination and a second end of each column in a source region and a drain region that are maximally replaced through the column. A nonvolatile memory formed with a termination, wherein at least the first termination is individually connected to each bit line. The non-volatile memory according to claim 8 or 18 ,
Charge storage element of one pair of non-volatile memory that extends in the second direction in the second opposed walls of each trench. The non-volatile memory according to claim 1.
A non-volatile memory further comprising additional source and drain regions disposed in the semiconductor material along a top surface between the trenches in a second direction. A method for producing a nonvolatile memory cell array on a semiconductor substrate,
Forming a first set of trenches in a surface of the substrate spaced in a first direction and extended in a second direction across the substrate surface, wherein the first direction and the second direction are: Steps that are perpendicular to each other;
Forming a source region and a drain region along the length of the trench on at least the bottom surface of the first set of trenches;
Isotropically depositing a first material on and in the first set of trenches;
The step of anisotropically removing the deposited first material to leave a spacer along the opposing sidewalls of the first set of trenches with a space between the sidewalls in a first direction. The spacer serves as a charge storage element of the memory cell array;
A first conductive control gate line extending in a second direction is formed on the first control gate to which the first conductive control gate line is electrically connected, and a first trench is formed between the spacers. Forming a first conductive control gate extending in a second direction within a space in the set of:
Including methods. 24. The method of claim 23.
Forming a second material between the trenches in at least a first direction prior to depositing the first material;
Then depositing the first material on the second material and on the first set of trenches and in the first set of trenches;
Removing the deposited first material anisotropically to leave spacers along opposing sidewalls of the trench and walls of the second material on the trench;
Then removing the deposited second material, thereby leaving a spacer extending a distance on the surface of the substrate;
A method further comprising: 25. The method of claim 24, wherein
A second control gate line extending in the first direction over the second control gate to which the second control gate line is electrically connected is formed in the space between the trenches in the first direction. Forming a second conductive control gate, the second control gate including both a substrate surface between the trenches in a first direction and a charge storage element extending a distance on the surface of the substrate. A method formed to be field coupled. 26. The method of claim 25, wherein
The second control gate and the second control gate line are formed as a single structure by a common process. 24. The method of claim 23.
The step of depositing the first material includes the step of depositing polysilicon, and the spacer of the charge storage element resulting from the polysilicon becomes a conductive floating gate. A method for producing a nonvolatile memory cell array on a semiconductor substrate,
Forming trenches in the surface of the substrate spaced apart in a first direction and extending in a second direction across the substrate surface, wherein the first direction and the second direction are perpendicular to each other A step and
Forming a source region and a drain region along the length of the trench at least on the bottom surface of the trench;
Depositing a first polysilicon material over the substrate and in the first set of trenches;
Removing the deposited first polysilicon material anisotropically so as to leave a conductive spacer along the opposing sidewalls of the trench with a space therebetween in a first direction;
Forming a control gate in the space between the spacers;
Separating the spacer into floating gates;
Forming a select gate on the substrate surface between the trenches in a first direction and connecting the select gate to a word line extending in the first direction and spaced in a second direction;
Including methods. A method for producing a nonvolatile memory cell array on a semiconductor substrate,
Forming in the surface of the substrate a first set of trenches spaced in a first direction and extending in a second direction across the substrate surface, the first direction and the second direction Steps whose directions are perpendicular to each other;
Forming a source region and a drain region along the length of the trench on at least the bottom surface of the first set of trenches;
Depositing a first polysilicon material over the substrate and in the first set of trenches;
Deposition so as to leave a region in the first set of trenches along the opposing sidewalls that does not extend outside the trench in the first direction but leaves a space between the polysilicon regions in the first direction. Removing the formed first polysilicon material anisotropically;
Forming a second polysilicon material in a space in the first set of trenches;
Forming a second set of trenches in a first polysilicon material and a second polysilicon material extending in a substrate surface and a second direction and spaced in a first direction, the method comprising: The depth of the second trench set is equal to the depth of the first trench set, thereby separating the sidewall regions of the first polysilicon into individual floating gates;
Forming a conductor material in the second set of trenches between the floating gates in a second direction;
A second polysilicon material in the first set of trenches and a second set of trenches in the first set of trenches, forming a strip of conductive material extending in the second direction and spaced in the first direction; Passing and contacting the conductive material;
Forming a select gate on a substrate surface between a set of first trenches in a first direction, the select gate extending in a first direction and spaced apart in a second direction Connecting to
Including methods. 24. The method of claim 23.
The step of forming the first conductive control gate and the first conductive control gate line includes electrically connecting the first conductive control gate and the first conductive control gate line. Method. 24. The method of claim 23.
Forming a select gate outside the trench in a first direction and connecting the select gate to a word line extending in the first direction and spaced in a second direction.

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