JP4895183B2 - メモリコントローラ - Google Patents

メモリコントローラ Download PDF

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Publication number
JP4895183B2
JP4895183B2 JP2006199943A JP2006199943A JP4895183B2 JP 4895183 B2 JP4895183 B2 JP 4895183B2 JP 2006199943 A JP2006199943 A JP 2006199943A JP 2006199943 A JP2006199943 A JP 2006199943A JP 4895183 B2 JP4895183 B2 JP 4895183B2
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JP
Japan
Prior art keywords
memory controller
memory
bus
command
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006199943A
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English (en)
Japanese (ja)
Other versions
JP2008027247A5 (enExample
JP2008027247A (ja
Inventor
武史 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2006199943A priority Critical patent/JP4895183B2/ja
Priority to PCT/JP2007/063041 priority patent/WO2008010397A1/ja
Priority to US12/304,749 priority patent/US8019951B2/en
Publication of JP2008027247A publication Critical patent/JP2008027247A/ja
Publication of JP2008027247A5 publication Critical patent/JP2008027247A5/ja
Application granted granted Critical
Publication of JP4895183B2 publication Critical patent/JP4895183B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP2006199943A 2006-07-21 2006-07-21 メモリコントローラ Expired - Fee Related JP4895183B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006199943A JP4895183B2 (ja) 2006-07-21 2006-07-21 メモリコントローラ
PCT/JP2007/063041 WO2008010397A1 (fr) 2006-07-21 2007-06-28 Contrôleur de mémoire
US12/304,749 US8019951B2 (en) 2006-07-21 2007-06-28 Memory controller including multiple system bus interfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006199943A JP4895183B2 (ja) 2006-07-21 2006-07-21 メモリコントローラ

Publications (3)

Publication Number Publication Date
JP2008027247A JP2008027247A (ja) 2008-02-07
JP2008027247A5 JP2008027247A5 (enExample) 2009-09-03
JP4895183B2 true JP4895183B2 (ja) 2012-03-14

Family

ID=38956732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006199943A Expired - Fee Related JP4895183B2 (ja) 2006-07-21 2006-07-21 メモリコントローラ

Country Status (3)

Country Link
US (1) US8019951B2 (enExample)
JP (1) JP4895183B2 (enExample)
WO (1) WO2008010397A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5019573B2 (ja) 2006-10-18 2012-09-05 キヤノン株式会社 メモリ制御回路とメモリシステム、及びそのメモリ制御方法、及び集積回路
US8239629B2 (en) * 2009-03-31 2012-08-07 Micron Technology, Inc. Hierarchical memory architecture to connect mass storage devices
JP2010252090A (ja) * 2009-04-16 2010-11-04 Rohm Co Ltd 半導体装置
JP2012128627A (ja) * 2010-12-15 2012-07-05 Toshiba Corp データ転送システム
US8635416B1 (en) * 2011-03-02 2014-01-21 Violin Memory Inc. Apparatus, method and system for using shadow drives for alternative drive commands
CN102591817B (zh) * 2011-12-30 2014-12-31 中山大学 一种多总线桥控制器及其实现方法
US9146690B2 (en) * 2012-01-27 2015-09-29 Marvell World Trade Ltd. Systems and methods for dynamic priority control
US9190133B2 (en) * 2013-03-11 2015-11-17 Micron Technology, Inc. Apparatuses and methods for a memory die architecture including an interface memory
JP6058122B2 (ja) * 2013-03-25 2017-01-11 三菱電機株式会社 バスマスタ、バスシステム及びバス制御方法
US9465754B2 (en) * 2013-06-28 2016-10-11 Analog Devices, Inc. Bridge circuit to arbitrate bus commands
TWI553483B (zh) * 2014-10-13 2016-10-11 瑞昱半導體股份有限公司 處理器及存取記憶體的方法
US10152237B2 (en) 2016-05-05 2018-12-11 Micron Technology, Inc. Non-deterministic memory protocol
US10534540B2 (en) 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
US11003602B2 (en) * 2017-01-24 2021-05-11 Micron Technology, Inc. Memory protocol with command priority

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11120154A (ja) 1997-10-20 1999-04-30 Fujitsu Ltd コンピュータシステムにおけるアクセス制御装置および方法
JP2000047974A (ja) * 1998-07-27 2000-02-18 Fujitsu Ltd バス制御コントローラのバス調停方法、バス制御コントローラ及び電子機器のシステム
JP2000148576A (ja) * 1998-11-06 2000-05-30 Nec Corp ファイル管理システム
US6779063B2 (en) * 2001-04-09 2004-08-17 Hitachi, Ltd. Direct access storage system having plural interfaces which permit receipt of block and file I/O requests
JP3918145B2 (ja) * 2001-05-21 2007-05-23 株式会社ルネサステクノロジ メモリコントローラ
JP2005316546A (ja) * 2004-04-27 2005-11-10 Victor Co Of Japan Ltd メモリコントローラ
JP2006099895A (ja) * 2004-09-30 2006-04-13 Canon Inc メモリ処理装置
JP4111192B2 (ja) * 2004-12-28 2008-07-02 セイコーエプソン株式会社 メモリコントローラ、表示コントローラ及びメモリ制御方法
US7755951B2 (en) * 2006-09-01 2010-07-13 Canon Kabushiki Kaisha Data output apparatus, memory system, data output method, and data processing method

Also Published As

Publication number Publication date
US8019951B2 (en) 2011-09-13
US20090138665A1 (en) 2009-05-28
JP2008027247A (ja) 2008-02-07
WO2008010397A1 (fr) 2008-01-24

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