JP4863836B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4863836B2 JP4863836B2 JP2006285713A JP2006285713A JP4863836B2 JP 4863836 B2 JP4863836 B2 JP 4863836B2 JP 2006285713 A JP2006285713 A JP 2006285713A JP 2006285713 A JP2006285713 A JP 2006285713A JP 4863836 B2 JP4863836 B2 JP 4863836B2
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- electrode
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
電子材料(1998年9月号22頁〜)の特集「CSP技術とそれを支える実装材料・装置」
まず本発明の半導体装置について図1を参照しながら説明する。尚、図1Aは半導体装置の平面図であり、図1Bは、A−A線の断面図である。
本製造方法は、図1の半導体装置15の製造方法を示すものであり、図2から図6は、図1AのA−A線に対応する断面図である。
図9に本半導体装置40を示す。図9Aは、その平面図であり、図9Bは、A−A線に於ける断面図である。
11A パッド
11B 配線
11C 外部接続電極
11D 放熱用の電極
12 半導体素子
13 ボンディング電極
14 分離溝
16 絶縁被膜
17 露出部
AF アンダーフィル材
Claims (4)
- 半導体チップがフェイスダウンで設けられ、前記半導体チップの裏面も含めて絶縁性樹脂に封止され、アイランド状の導電パターンが前記絶縁性樹脂に埋め込まれた半導体装置であり、
前記絶縁性樹脂から成るパッケージの裏面の中央に露出して設けられ、前記導電パターンの一つである複数に分割された第1の電極と、前記第1の電極の周囲を囲み、前記半導体チップのボンディング電極と対応して設けられ、前記パッケージ裏面から露出し、前記第1の電極よりもサイズが小さく設けられた、外部接続電極と成る前記導電パターンの一つである複数の第2の電極とを有し、
前記パッケージの裏面には絶縁被膜が設けられ、前記絶縁被膜から露出した前記第1の電極および前記第2の電極にはロウ材または導電ペーストが設けられ、
前記絶縁被膜から露出する開口部を実質同一サイズとする事で、前記第1の電極および前記第2の電極に設けられるロウ材の高さを実質同一にした事を特徴とする半導体装置。 - 前記半導体チップと前記第1の電極との間にアンダーフィル材が設けられ、前記アンダーフィル材は、複数に分割された前記第1の電極と隣の前記第1の電極との間に充填される請求項1に記載の半導体装置。
- 前記第1の電極は、放熱電極として機能する請求項1または請求項2に記載の半導体装置。
- 前記第2の電極の裏面形状は矩形で、前記絶縁被膜から露出する前記第1の電極および前記第2の電極は、前記矩形で且つ同一パターンで形成される請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006285713A JP4863836B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006285713A JP4863836B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000269464A Division JP3945968B2 (ja) | 2000-09-06 | 2000-09-06 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007013219A JP2007013219A (ja) | 2007-01-18 |
JP4863836B2 true JP4863836B2 (ja) | 2012-01-25 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006285713A Expired - Lifetime JP4863836B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置 |
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JP (1) | JP4863836B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10950558B2 (en) | 2017-03-27 | 2021-03-16 | Mitsubishi Electric Corporation | Semiconductor device, power converter, and method for manufacturing semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10321670A (ja) * | 1997-05-21 | 1998-12-04 | Hitachi Ltd | 半導体装置 |
JP3947292B2 (ja) * | 1998-02-10 | 2007-07-18 | 大日本印刷株式会社 | 樹脂封止型半導体装置の製造方法 |
JP3481117B2 (ja) * | 1998-02-25 | 2003-12-22 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP2000068436A (ja) * | 1998-08-18 | 2000-03-03 | Oki Electric Ind Co Ltd | 半導体装置および半導体装置用フレーム |
JP3965813B2 (ja) * | 1999-01-26 | 2007-08-29 | 松下電器産業株式会社 | ターミナルランドフレームの製造方法 |
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2006
- 2006-10-20 JP JP2006285713A patent/JP4863836B2/ja not_active Expired - Lifetime
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