JP4837586B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4837586B2
JP4837586B2 JP2007019295A JP2007019295A JP4837586B2 JP 4837586 B2 JP4837586 B2 JP 4837586B2 JP 2007019295 A JP2007019295 A JP 2007019295A JP 2007019295 A JP2007019295 A JP 2007019295A JP 4837586 B2 JP4837586 B2 JP 4837586B2
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JP
Japan
Prior art keywords
phase
signal
shift amount
register
phase shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007019295A
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English (en)
Japanese (ja)
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JP2008186517A5 (enExample
JP2008186517A (ja
Inventor
大 原口
徳哉 大澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2007019295A priority Critical patent/JP4837586B2/ja
Priority to US12/010,674 priority patent/US7983112B2/en
Publication of JP2008186517A publication Critical patent/JP2008186517A/ja
Publication of JP2008186517A5 publication Critical patent/JP2008186517A5/ja
Application granted granted Critical
Publication of JP4837586B2 publication Critical patent/JP4837586B2/ja
Expired - Fee Related legal-status Critical Current
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry

Landscapes

  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP2007019295A 2007-01-30 2007-01-30 半導体装置 Expired - Fee Related JP4837586B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007019295A JP4837586B2 (ja) 2007-01-30 2007-01-30 半導体装置
US12/010,674 US7983112B2 (en) 2007-01-30 2008-01-29 Semiconductor device which transmits or receives a signal to or from an external memory by a DDR system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007019295A JP4837586B2 (ja) 2007-01-30 2007-01-30 半導体装置

Publications (3)

Publication Number Publication Date
JP2008186517A JP2008186517A (ja) 2008-08-14
JP2008186517A5 JP2008186517A5 (enExample) 2010-02-25
JP4837586B2 true JP4837586B2 (ja) 2011-12-14

Family

ID=39667810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007019295A Expired - Fee Related JP4837586B2 (ja) 2007-01-30 2007-01-30 半導体装置

Country Status (2)

Country Link
US (1) US7983112B2 (enExample)
JP (1) JP4837586B2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4785465B2 (ja) * 2005-08-24 2011-10-05 ルネサスエレクトロニクス株式会社 インタフェース回路及び半導体装置
US7836372B2 (en) 2007-06-08 2010-11-16 Apple Inc. Memory controller with loopback test interface
US8234422B2 (en) * 2009-09-11 2012-07-31 Avago Technologies Enterprise IP (Singapore) Pte. Ltd Interfaces, circuits, and methods for communicating with a double data rate memory device
US8279697B2 (en) 2009-09-11 2012-10-02 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus
JP5314612B2 (ja) * 2010-02-04 2013-10-16 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP2012027734A (ja) * 2010-07-23 2012-02-09 Panasonic Corp メモリコントローラおよびメモリアクセスシステム
KR102336455B1 (ko) 2015-01-22 2021-12-08 삼성전자주식회사 집적 회로 및 집적 회로를 포함하는 스토리지 장치
KR102371893B1 (ko) * 2017-05-18 2022-03-08 삼성전자주식회사 반도체 메모리 칩, 반도체 메모리 패키지, 및 이를 이용한 전자 시스템
EP3557786A1 (en) 2018-04-16 2019-10-23 Samsung Electronics Co., Ltd. Method of testing rf integrated circuit

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
JP3483437B2 (ja) 1997-08-29 2004-01-06 富士通株式会社 半導体装置及びその試験方法
KR100303775B1 (ko) * 1998-10-28 2001-09-24 박종섭 디디알 에스디램에서 데이터스트로브신호를 제어하기 위한 방법및 장치
JP2000187612A (ja) * 1998-12-22 2000-07-04 Nkk Corp データフェッチタイミング切り替え回路
US6615345B1 (en) * 1999-07-29 2003-09-02 Micron Technology, Inc. System and method for regulating data capture in response to data strobe using preamble, postamble and strobe signature
US7002378B2 (en) * 2000-12-29 2006-02-21 Intel Corporation Valid data strobe detection technique
JP2003173290A (ja) * 2001-12-06 2003-06-20 Ricoh Co Ltd メモリ制御装置
US7117382B2 (en) * 2002-05-30 2006-10-03 Sun Microsystems, Inc. Variably controlled delay line for read data capture timing window
KR100626375B1 (ko) * 2003-07-21 2006-09-20 삼성전자주식회사 고주파로 동작하는 반도체 메모리 장치 및 모듈
US7259606B2 (en) * 2004-01-27 2007-08-21 Nvidia Corporation Data sampling clock edge placement training for high speed GPU-memory interface
JP4785465B2 (ja) * 2005-08-24 2011-10-05 ルネサスエレクトロニクス株式会社 インタフェース回路及び半導体装置
JP4878215B2 (ja) * 2006-05-26 2012-02-15 ルネサスエレクトロニクス株式会社 インタフェース回路及びメモリ制御装置
US7685393B2 (en) * 2006-06-30 2010-03-23 Mosaid Technologies Incorporated Synchronous memory read data capture
US7652932B2 (en) * 2007-07-19 2010-01-26 Mosaid Technologies Incorporated Memory system having incorrupted strobe signals

Also Published As

Publication number Publication date
US7983112B2 (en) 2011-07-19
US20080181047A1 (en) 2008-07-31
JP2008186517A (ja) 2008-08-14

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