JP4799868B2 - 半導体装置の形成方法およびその構造 - Google Patents

半導体装置の形成方法およびその構造 Download PDF

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Publication number
JP4799868B2
JP4799868B2 JP2004564756A JP2004564756A JP4799868B2 JP 4799868 B2 JP4799868 B2 JP 4799868B2 JP 2004564756 A JP2004564756 A JP 2004564756A JP 2004564756 A JP2004564756 A JP 2004564756A JP 4799868 B2 JP4799868 B2 JP 4799868B2
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Japan
Prior art keywords
dielectric layer
passivation film
conductive region
conductive
dummy
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Expired - Lifetime
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JP2004564756A
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English (en)
Japanese (ja)
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JP2006511955A5 (enExample
JP2006511955A (ja
Inventor
ケイ． ゴールドバーグ、シンディ
エム． フィリピアク、スタンリー
シー． フレイク、ジョン
ティ． リー、ヨン−ジー
ピー． スミス、ブラッドリー
イー． ソロメンツェフ、ユーリ
ジー． スパークス、テリー
ジェイ． ストロゼウスキー、カーク
シー． ユー、キャスリーン
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2004564756A 2002-12-20 2003-09-23 半導体装置の形成方法およびその構造 Expired - Lifetime JP4799868B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/327,403 2002-12-20
US10/327,403 US6838354B2 (en) 2002-12-20 2002-12-20 Method for forming a passivation layer for air gap formation
PCT/US2003/030590 WO2004061948A2 (en) 2002-12-20 2003-09-23 Method for forming a semiconductor device and structure thereof

Related Child Applications (1)

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JP2006213013A Division JP4794389B2 (ja) 2002-12-20 2006-08-04 半導体装置の形成方法およびその構造

Publications (3)

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JP2006511955A JP2006511955A (ja) 2006-04-06
JP2006511955A5 JP2006511955A5 (enExample) 2006-09-21
JP4799868B2 true JP4799868B2 (ja) 2011-10-26

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JP2004564756A Expired - Lifetime JP4799868B2 (ja) 2002-12-20 2003-09-23 半導体装置の形成方法およびその構造
JP2006213013A Expired - Lifetime JP4794389B2 (ja) 2002-12-20 2006-08-04 半導体装置の形成方法およびその構造

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US (1) US6838354B2 (enExample)
EP (1) EP1579497A3 (enExample)
JP (2) JP4799868B2 (enExample)
KR (1) KR20050085833A (enExample)
CN (1) CN100378948C (enExample)
AU (1) AU2003279030A1 (enExample)
TW (1) TWI367543B (enExample)
WO (1) WO2004061948A2 (enExample)

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US20050147746A1 (en) * 2003-12-30 2005-07-07 Dubin Valery M. Nanotube growth and device formation
US7405147B2 (en) 2004-01-30 2008-07-29 International Business Machines Corporation Device and methodology for reducing effective dielectric constant in semiconductor devices
JP2006031875A (ja) * 2004-07-20 2006-02-02 Fujitsu Ltd 記録媒体基板および記録媒体
US20060038293A1 (en) * 2004-08-23 2006-02-23 Rueger Neal R Inter-metal dielectric fill
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KR101382564B1 (ko) * 2008-05-28 2014-04-10 삼성전자주식회사 에어갭을 갖는 층간 절연막의 형성 방법
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Also Published As

Publication number Publication date
CN100378948C (zh) 2008-04-02
US6838354B2 (en) 2005-01-04
WO2004061948A2 (en) 2004-07-22
JP2006324689A (ja) 2006-11-30
JP2006511955A (ja) 2006-04-06
TWI367543B (en) 2012-07-01
AU2003279030A1 (en) 2004-07-29
CN1820365A (zh) 2006-08-16
WO2004061948A3 (en) 2005-10-13
US20040119134A1 (en) 2004-06-24
JP4794389B2 (ja) 2011-10-19
TW200414414A (en) 2004-08-01
EP1579497A3 (en) 2005-12-07
EP1579497A2 (en) 2005-09-28
KR20050085833A (ko) 2005-08-29

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