JP4789421B2 - フォトン吸収膜を有する半導体素子及びその製造方法 - Google Patents
フォトン吸収膜を有する半導体素子及びその製造方法 Download PDFInfo
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- JP4789421B2 JP4789421B2 JP2004069820A JP2004069820A JP4789421B2 JP 4789421 B2 JP4789421 B2 JP 4789421B2 JP 2004069820 A JP2004069820 A JP 2004069820A JP 2004069820 A JP2004069820 A JP 2004069820A JP 4789421 B2 JP4789421 B2 JP 4789421B2
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- 239000004065 semiconductor Substances 0.000 title claims description 61
- 238000000034 method Methods 0.000 title claims description 47
- 238000010521 absorption reaction Methods 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- 239000011229 interlayer Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 31
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 22
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 description 147
- 230000008569 process Effects 0.000 description 18
- 239000010410 layer Substances 0.000 description 14
- 229910052732 germanium Inorganic materials 0.000 description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000008033 biological extinction Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- -1 germanium (Ge) Chemical compound 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 229910021350 transition metal silicide Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
また、前記本発明の目的を達成するために、本発明の一見地による半導体素子の製造方法は、半導体基板上にMOSトランジスタを形成する段階と、前記MOSトランジスタ及び半導体基板の上部にエッチストッパーを形成する段階と、前記エッチストッパーの上部にシリコンゲルマニウム膜を形成し当該シリコンゲルマニウム膜の上部にシリコン膜を積層して形成した積層膜よりなるフォトン吸収膜を形成する段階と、前記フォトン吸収膜の上部にHDP方式によって層間絶縁膜を形成する段階と、を含むことを特徴とする。
α=4πk/λ 式2
前記式1及び2で、Iは出射光、I0は入射光、αは吸収係数、kは吸光係数及びdは媒質の厚さを表す。前記式1及び式2によれば、吸収係数αは、吸光係数kと比例し、吸収係数αが増大するほど出射光が指数関数的に減少して、多量の光が吸収される。
ここで、Eはエネルギー、hはフランク定数、νは光の振動数、cは光の速度及びλは光の波長を意味する。
110 ゲート絶縁膜、
115 ゲート電極用導電層、
120 ハードマスク膜、
125 スペーサ、
130a,130b 接合領域、
140 エッチストッパー、
145 シリコン膜、
g ゲート電極構造物、
146 シリコンゲルマニウム膜、
147 フォトン吸収膜、
150 層間絶縁膜。
Claims (4)
- 半導体基板上にMOSトランジスタを形成する段階と、
前記MOSトランジスタ及び半導体基板の上部にエッチストッパーを形成する段階と、
前記エッチストッパーの上部にシリコン膜を形成し当該シリコン膜の上部にシリコンゲルマニウム膜を積層して形成した積層膜よりなるフォトン吸収膜を形成する段階と、
前記フォトン吸収膜の上部にHDP方式によって層間絶縁膜を形成する段階と、
を含むことを特徴とする半導体素子の製造方法。 - 半導体基板上にMOSトランジスタを形成する段階と、
前記MOSトランジスタ及び半導体基板の上部にエッチストッパーを形成する段階と、
前記エッチストッパーの上部にシリコンゲルマニウム膜を形成し当該シリコンゲルマニウム膜の上部にシリコン膜を積層して形成した積層膜よりなるフォトン吸収膜を形成する段階と、
前記フォトン吸収膜の上部にHDP方式によって層間絶縁膜を形成する段階と、
を含むことを特徴とする半導体素子の製造方法。 - 請求項1または2に記載の半導体素子の製造方法を用いて形成される半導体素子であって、
半導体基板と、
前記半導体基板上の所定部分に形成されたMOSトランジスタと、
前記MOSトランジスタ及び半導体基板を覆うように形成されるエッチストッパーと、
前記エッチストッパーの上部に形成されるフォトン吸収膜と、
前記フォトン吸収膜の上部に形成される層間絶縁膜と、を含み、
前記フォトン吸収膜は、シリコン膜とシリコンゲルマニウム膜の積層膜であることを特徴とする半導体素子。 - 前記エッチストパーは、前記層間絶縁膜とエッチング選択比が異なるエッチストッパーであることを特徴とする請求項3に記載の半導体素子。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2003-015393 | 2003-03-12 | ||
KR1020030015393A KR100574939B1 (ko) | 2003-03-12 | 2003-03-12 | 포톤 흡수막을 갖는 반도체 소자 및 그 제조방법 |
US10/740,570 US7026662B2 (en) | 2003-03-12 | 2003-12-22 | Semiconductor device having a photon absorption layer to prevent plasma damage |
US10/740,570 | 2003-12-22 |
Publications (2)
Publication Number | Publication Date |
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JP2004282069A JP2004282069A (ja) | 2004-10-07 |
JP4789421B2 true JP4789421B2 (ja) | 2011-10-12 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2004069820A Expired - Lifetime JP4789421B2 (ja) | 2003-03-12 | 2004-03-11 | フォトン吸収膜を有する半導体素子及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20060145183A1 (ja) |
JP (1) | JP4789421B2 (ja) |
CN (1) | CN100456492C (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100540061B1 (ko) * | 2003-12-31 | 2005-12-29 | 동부아남반도체 주식회사 | 플라즈마 데미지를 방지하는 방법 |
KR100617067B1 (ko) * | 2005-06-27 | 2006-08-30 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그의 제조방법 |
US20070010073A1 (en) * | 2005-07-06 | 2007-01-11 | Chien-Hao Chen | Method of forming a MOS device having a strained channel region |
KR100864932B1 (ko) * | 2007-07-23 | 2008-10-22 | 주식회사 동부하이텍 | 반도체 기판의 세정방법 |
CN101640175B (zh) * | 2008-07-31 | 2012-10-10 | 中芯国际集成电路制造(北京)有限公司 | 半导体结构的制造方法 |
CN103035564B (zh) * | 2011-09-29 | 2015-03-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制造方法 |
CN103050393B (zh) * | 2011-10-17 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | 原子层级的等离子体刻蚀方法 |
KR20130086663A (ko) | 2012-01-26 | 2013-08-05 | 삼성전자주식회사 | 반도체 소자 |
Family Cites Families (18)
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JPH0414226A (ja) * | 1990-05-07 | 1992-01-20 | Toshiba Corp | 半導体装置の製造方法 |
JPH04296017A (ja) * | 1991-03-25 | 1992-10-20 | Nikon Corp | 半導体装置の製造方法 |
JP2905314B2 (ja) * | 1991-07-08 | 1999-06-14 | シャープ株式会社 | 半導体装置の製造方法 |
US5369040A (en) * | 1992-05-18 | 1994-11-29 | Westinghouse Electric Corporation | Method of making transparent polysilicon gate for imaging arrays |
US5480814A (en) * | 1994-12-27 | 1996-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process of making a polysilicon barrier layer in a self-aligned contact module |
JP2616741B2 (ja) * | 1995-04-27 | 1997-06-04 | 日本電気株式会社 | 多結晶シリコン−ゲルマニウム薄膜トランジスタの製造方法 |
KR100224720B1 (ko) * | 1996-10-31 | 1999-10-15 | 윤종용 | 반도체장치의 콘택홀 형성방법 |
JPH10256536A (ja) * | 1997-03-17 | 1998-09-25 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2000216137A (ja) * | 1999-01-18 | 2000-08-04 | United Microelectronics Corp | プラズマ充電損傷および垂直漏話を防止するデバイス保護構造 |
US6410210B1 (en) * | 1999-05-20 | 2002-06-25 | Philips Semiconductors | Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides |
US6645837B2 (en) * | 2000-05-31 | 2003-11-11 | Sony Corporation | Method of manufacturing semiconductor device |
US6365446B1 (en) * | 2000-07-03 | 2002-04-02 | Chartered Semiconductor Manufacturing Ltd. | Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process |
JP2002050764A (ja) * | 2000-08-02 | 2002-02-15 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ、アレイ基板、液晶表示装置、有機el表示装置およびその製造方法 |
US6440811B1 (en) * | 2000-12-21 | 2002-08-27 | International Business Machines Corporation | Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme |
JP2003059854A (ja) * | 2001-08-13 | 2003-02-28 | Toshiba Corp | 光加熱装置、光加熱方法及び半導体装置の製造方法 |
JP3986781B2 (ja) * | 2001-08-28 | 2007-10-03 | 株式会社半導体エネルギー研究所 | 薄膜トランジスタの作製方法 |
US6919219B2 (en) * | 2002-11-21 | 2005-07-19 | Texas Instruments Incorporated | Photon-blocking layer |
JP2004172617A (ja) * | 2002-11-21 | 2004-06-17 | Texas Instr Inc <Ti> | 光子阻止層 |
-
2004
- 2004-03-11 JP JP2004069820A patent/JP4789421B2/ja not_active Expired - Lifetime
- 2004-03-12 CN CNB2004100595371A patent/CN100456492C/zh not_active Expired - Lifetime
-
2006
- 2006-03-06 US US11/367,420 patent/US20060145183A1/en not_active Abandoned
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Publication number | Publication date |
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US20060145183A1 (en) | 2006-07-06 |
JP2004282069A (ja) | 2004-10-07 |
CN1542985A (zh) | 2004-11-03 |
CN100456492C (zh) | 2009-01-28 |
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