JP4789406B2 - 入/出力の帯域幅を調節可能なメモリ装置 - Google Patents
入/出力の帯域幅を調節可能なメモリ装置 Download PDFInfo
- Publication number
- JP4789406B2 JP4789406B2 JP2003297754A JP2003297754A JP4789406B2 JP 4789406 B2 JP4789406 B2 JP 4789406B2 JP 2003297754 A JP2003297754 A JP 2003297754A JP 2003297754 A JP2003297754 A JP 2003297754A JP 4789406 B2 JP4789406 B2 JP 4789406B2
- Authority
- JP
- Japan
- Prior art keywords
- data input
- output buffer
- signal
- switch
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/108—Wide data ports
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Description
12 カラム選択制御部
13 メインビットライン負荷制御部
21 データバス部
30 センスアンプアレイ
31、510 下位バイト領域
32、520 上位バイト領域
100 セルアレイブロック
110 サブセルブロック
200 カラムディコーダ
300 スイッチ制御部
400 スイッチアレイ
410 第1のスイッチ
420 第2のスイッチ
430 第3のスイッチ
500 データ入/出力バッファ
600、610、620 データパッド
Claims (2)
- 強誘電体メモリを含み、それぞれ複数のメモリセルが連結された複数のサブビットラインと、それぞれ前記複数のサブビットラインが連結された複数のメインビットラインを含んで二重化した構造からなり、前記サブビットラインの電圧により前記メインビットラインに流れる電流の大きさを決定する電流調節用トランジスタを含むサブセルブロック、
下位バイト領域に属するデータ入/出力バッファと同下位バイト領域に属するセンスアンプアレイとを連結する複数の第1のスイッチ、前記下位バイト領域に属するデータ入/出力バッファと上位バイト領域に属するセンスアンプアレイとを連結する複数の第2のスイッチ、前記上位バイト領域に属するデータ入/出力バッファと同上位バイト領域に属するセンスアンプアレイとを連結する複数の第3のスイッチを含むスイッチアレイ、
外部制御信号を受信して前記各データ入/出力バッファの活性化の可否と前記第1〜第3のスイッチのオン/オフを制御するスイッチ制御部、及び
前記サブセルブロックと前記各センスアンプアレイとの間でデータを交換するデータバス部を備え、
前記スイッチ制御部が、前記外部制御信号に含まれたバイト信号が活性化された場合は、前記データ入/出力バッファの上位バイト領域を非活性化した後、前記データ入/出力バッファの上位バイト領域と連結された端子ピンを介して入力された信号が「1」であれば前記第2のスイッチを活性化し、前記端子ピンを介して入力された信号が「0」であれば前記第1のスイッチを活性化し、前記バイト信号が非活性化された場合は、前記外部制御信号に含まれた下位バイト信号が活性化されると前記第1のスイッチをオン状態にして、前記データ入/出力バッファの下位バイト領域を活性化し、前記外部制御信号に含まれた上位バイト信号が活性化されると前記第3のスイッチをオン状態にして、前記データ入/出力バッファの上位バイト領域を活性化することを特徴とするメモリ装置。 - 前記データ入/出力バッファの下位バイト領域が複数のデータビットを入/出力する入/出力ポートと連結され、前記データ入/出力バッファの上位バイト領域が前記データ入/出力ポートと連結されていない状態にて、前記データ入/出力バッファの前記端子ピンを介して提供される信号を、前記外部制御信号の1つとして用いることを特徴とする請求項1に記載のメモリ装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0079722A KR100527529B1 (ko) | 2002-12-13 | 2002-12-13 | 입출력 대역폭을 조절할 수 있는 메모리 장치 |
KR2002-079722 | 2002-12-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004199849A JP2004199849A (ja) | 2004-07-15 |
JP4789406B2 true JP4789406B2 (ja) | 2011-10-12 |
Family
ID=36125353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003297754A Expired - Fee Related JP4789406B2 (ja) | 2002-12-13 | 2003-08-21 | 入/出力の帯域幅を調節可能なメモリ装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7006387B2 (ja) |
JP (1) | JP4789406B2 (ja) |
KR (1) | KR100527529B1 (ja) |
CN (1) | CN100495708C (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100532471B1 (ko) | 2003-09-26 | 2005-12-01 | 삼성전자주식회사 | 입출력 데이터 위스 조절이 가능한 메모리 장치 및 그위스 조절 방법 |
KR101062776B1 (ko) * | 2010-01-29 | 2011-09-06 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
US8830716B2 (en) * | 2012-09-29 | 2014-09-09 | Intel Corporation | Intelligent far memory bandwith scaling |
Family Cites Families (29)
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US4447878A (en) * | 1978-05-30 | 1984-05-08 | Intel Corporation | Apparatus and method for providing byte and word compatible information transfers |
JPS62192085A (ja) * | 1986-02-18 | 1987-08-22 | Matsushita Electric Ind Co Ltd | ビツト処理回路 |
JPS6369093A (ja) * | 1986-09-11 | 1988-03-29 | Fujitsu Ltd | 半導体メモリ装置 |
US4873664A (en) | 1987-02-12 | 1989-10-10 | Ramtron Corporation | Self restoring ferroelectric memory |
US5134584A (en) * | 1988-07-22 | 1992-07-28 | Vtc Incorporated | Reconfigurable memory |
US5301155A (en) * | 1990-03-20 | 1994-04-05 | Mitsubishi Denki Kabushiki Kaisha | Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits |
JPH04168697A (ja) * | 1990-10-31 | 1992-06-16 | Nec Corp | 半導体メモリ装置 |
US5404454A (en) * | 1991-02-28 | 1995-04-04 | Dell Usa, L.P. | Method for interleaving computer disk data input-out transfers with permuted buffer addressing |
US5373467A (en) * | 1993-11-10 | 1994-12-13 | Silicon Storage Technology, Inc. | Solid state memory device capable of providing data signals on 2N data lines or N data lines |
JPH08195079A (ja) * | 1995-01-11 | 1996-07-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5815456A (en) * | 1996-06-19 | 1998-09-29 | Cirrus Logic, Inc. | Multibank -- multiport memories and systems and methods using the same |
KR100239692B1 (ko) * | 1996-07-27 | 2000-01-15 | 김영환 | 반도체 장치의 출력회로 |
JPH10269784A (ja) | 1997-03-28 | 1998-10-09 | Rohm Co Ltd | 強誘電体メモリ |
JPH11224492A (ja) | 1997-11-06 | 1999-08-17 | Toshiba Corp | 半導体記憶装置、不揮発性半導体記憶装置及びフラッシュメモリ |
KR100258574B1 (ko) | 1997-12-30 | 2000-06-15 | 윤종용 | 반도체 메모리 장치 및 그 장치의 프로그램/소거 검증 방법 |
KR100280430B1 (ko) * | 1998-01-20 | 2001-02-01 | 김영환 | 데이터버퍼를이용하여데이터를읽는방법 |
US5896337A (en) * | 1998-02-23 | 1999-04-20 | Micron Technology, Inc. | Circuits and methods for multi-level data through a single input/ouput pin |
CN1202530C (zh) * | 1998-04-01 | 2005-05-18 | 三菱电机株式会社 | 在低电源电压下高速动作的静态型半导体存储装置 |
JP3961680B2 (ja) * | 1998-06-30 | 2007-08-22 | 株式会社東芝 | 半導体記憶装置 |
JP2000076865A (ja) * | 1998-08-28 | 2000-03-14 | Kawasaki Steel Corp | 半導体記憶装置 |
KR100322540B1 (ko) * | 1999-07-14 | 2002-03-18 | 윤종용 | 입출력 센스앰프가 차지하는 면적을 최소화하는 메모리 장치 |
KR100304709B1 (ko) * | 1999-07-23 | 2001-11-01 | 윤종용 | 외부에서 데이터 입출력 모드를 제어할 수 있는 반도체 메모리장치 |
JP2001118377A (ja) * | 1999-10-19 | 2001-04-27 | Mitsubishi Electric Corp | 半導体装置 |
JP2002093159A (ja) * | 2000-09-08 | 2002-03-29 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR100381957B1 (ko) | 2001-01-04 | 2003-04-26 | 삼성전자주식회사 | 비휘발성 반도체 메모리 장치 및 그것의 데이터 입/출력제어 방법 |
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KR100447223B1 (ko) * | 2001-09-17 | 2004-09-04 | 주식회사 하이닉스반도체 | 불휘발성 강유전체 메모리 및 그 구동방법 |
US6873536B2 (en) * | 2002-04-19 | 2005-03-29 | Texas Instruments Incorporated | Shared data buffer in FeRAM utilizing word line direction segmentation |
-
2002
- 2002-12-13 KR KR10-2002-0079722A patent/KR100527529B1/ko not_active IP Right Cessation
-
2003
- 2003-07-30 US US10/629,671 patent/US7006387B2/en not_active Expired - Lifetime
- 2003-07-31 CN CNB031550193A patent/CN100495708C/zh not_active Expired - Fee Related
- 2003-08-21 JP JP2003297754A patent/JP4789406B2/ja not_active Expired - Fee Related
-
2005
- 2005-12-06 US US11/294,531 patent/US7663935B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20040114441A1 (en) | 2004-06-17 |
US7663935B2 (en) | 2010-02-16 |
US7006387B2 (en) | 2006-02-28 |
KR20040052006A (ko) | 2004-06-19 |
US20060072361A1 (en) | 2006-04-06 |
KR100527529B1 (ko) | 2005-11-09 |
CN100495708C (zh) | 2009-06-03 |
JP2004199849A (ja) | 2004-07-15 |
CN1507058A (zh) | 2004-06-23 |
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