JP2005537602A - メモリマトリクスの複数の横列に対して同時書き込みを行うデバイス - Google Patents
メモリマトリクスの複数の横列に対して同時書き込みを行うデバイス Download PDFInfo
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- JP2005537602A JP2005537602A JP2004532414A JP2004532414A JP2005537602A JP 2005537602 A JP2005537602 A JP 2005537602A JP 2004532414 A JP2004532414 A JP 2004532414A JP 2004532414 A JP2004532414 A JP 2004532414A JP 2005537602 A JP2005537602 A JP 2005537602A
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- power supply
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- 230000015654 memory Effects 0.000 title claims abstract description 71
- 239000011159 matrix material Substances 0.000 title claims abstract description 22
- 230000003068 static effect Effects 0.000 claims description 7
- 230000007423 decrease Effects 0.000 abstract description 4
- 230000005779 cell damage Effects 0.000 description 2
- 208000037887 cell injury Diseases 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007306 turnover Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
Claims (10)
- メモリを有するデバイスであって、
−横列および縦列に機能的に配置された複数のスタティックメモリセルから成るマトリクスと、
−それぞれが前記縦列の対応する1つにおける前記メモリセルに対してデータを書き込むビットライン回路と、
−複数の前記横列内の前記メモリセルを同時に選択して前記ビットラインドライバ回路から書き込みデータを受けるように構成されたワードライン回路と、
−前記セルに結合されるとともに、少なくとも複数の前記横列の前記メモリセル内へのデータの同時書き込み中に、前記個々のメモリセル内にデータを書き込むために必要なドライブ強度を前記ビットライン回路のドライブ強度に対して減少させるようになっているセル強度制御回路と、
を備えるデバイス。 - 前記セル強度制御回路は、共通電源と内部電源ラインとの間に結合された電源リダクション回路を備え、前記縦列のうちの少なくとも1つにおける前記メモリセルは前記内部電源ラインに結合された電源入力を有し、前記電源リダクション回路は、少なくとも前記メモリセル内へのデータの書き込み中に電源電圧降下を適時に与えるようになっている、請求項1に記載のデバイス。
- 前記電源リダクション回路は、前記共通電源と前記内部電源ラインとの間に結合された抵抗素子を備えている、請求項2に記載のデバイス。
- 前記抵抗素子は、主電流チャンネルが前記共通電源と前記内部電源ラインとの間に結合されたトランジスタを構成している、請求項2に記載のデバイス。
- 少なくとも1つの前記縦列における前記ビットライン回路は、前記内部電源ラインに結合された電源入力を有するビットラインドライバ回路を備えている、請求項2に記載のデバイス。
- 前記ビットラインドライバ回路は、前記共通電源ラインから得られかつ前記電源電圧降下によって実質的に影響されない制御電圧を受けるように結合された制御入力を有している、請求項5に記載のデバイス。
- 前記セル強度制御回路は、それぞれが共通電源と対応する内部電源ラインとの間に結合された複数の電源リダクション回路を備え、複数ある前記縦列のうちの対応する縦列内の前記メモリセルはそれぞれ前記内部電源ラインのうちの対応する1つに結合された電源入力を有し、前記各電源リダクション回路は、少なくとも前記メモリセル内へのデータの書き込み中に選択的に、それが結合される内部電源ラインのうちの対応する1つに対して対応する電源電圧降下を与えるようになっている、請求項1に記載のデバイス。
- 前記各電源リダクション回路は、前記共通電源と対応する前記内部電源ラインとの間に結合された抵抗素子を備えている、請求項7に記載のデバイス。
- 前記各縦列における前記ビットライン回路は、その対応する縦列の前記内部電源ラインに結合された電源入力を有する対応するビットラインドライバ回路を備えている、請求項7に記載のデバイス。
- 前記各ビットラインドライバ回路は、前記共通電源ラインから得られかつ前記電源電圧降下によって実質的に影響されない制御電圧を受けるように結合された制御入力を有している、請求項9に記載のデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02078590 | 2002-09-02 | ||
PCT/IB2003/003729 WO2004021353A1 (en) | 2002-09-02 | 2003-07-31 | Device writing to a plurality of rows in a memory matrix simultaneously |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005537602A true JP2005537602A (ja) | 2005-12-08 |
JP4262678B2 JP4262678B2 (ja) | 2009-05-13 |
Family
ID=31970374
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004532414A Expired - Fee Related JP4262678B2 (ja) | 2002-09-02 | 2003-07-31 | メモリマトリクスの複数の横列に対して同時書き込みを行うデバイス |
Country Status (6)
Country | Link |
---|---|
US (1) | US7474553B2 (ja) |
EP (1) | EP1537583A1 (ja) |
JP (1) | JP4262678B2 (ja) |
CN (1) | CN1679111B (ja) |
AU (1) | AU2003253205A1 (ja) |
WO (1) | WO2004021353A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014139860A (ja) * | 2014-03-28 | 2014-07-31 | Renesas Electronics Corp | 半導体集積回路装置 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4571798B2 (ja) * | 2001-06-12 | 2010-10-27 | バーゼル・ポリオレフィン・ゲーエムベーハー | 1−ブテンの重合方法 |
US7167025B1 (en) | 2004-02-14 | 2007-01-23 | Herman Schmit | Non-sequentially configurable IC |
US7425841B2 (en) | 2004-02-14 | 2008-09-16 | Tabula Inc. | Configurable circuits, IC's, and systems |
JP4553185B2 (ja) | 2004-09-15 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
US7330050B2 (en) | 2004-11-08 | 2008-02-12 | Tabula, Inc. | Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements |
US7317331B2 (en) | 2004-11-08 | 2008-01-08 | Tabula, Inc. | Reconfigurable IC that has sections running at different reconfiguration rates |
US7272031B1 (en) * | 2005-03-15 | 2007-09-18 | Tabula, Inc. | Method and apparatus for reduced power cell |
US7230869B1 (en) | 2005-03-15 | 2007-06-12 | Jason Redgrave | Method and apparatus for accessing contents of memory cells |
US7669097B1 (en) | 2006-03-27 | 2010-02-23 | Tabula, Inc. | Configurable IC with error detection and correction circuitry |
JP5158624B2 (ja) * | 2006-08-10 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7535252B1 (en) | 2007-03-22 | 2009-05-19 | Tabula, Inc. | Configurable ICs that conditionally transition through configuration data sets |
US7928761B2 (en) | 2007-09-06 | 2011-04-19 | Tabula, Inc. | Configuration context switcher with a latch |
US8238173B2 (en) * | 2009-07-16 | 2012-08-07 | Zikbit Ltd | Using storage cells to perform computation |
US9076527B2 (en) * | 2009-07-16 | 2015-07-07 | Mikamonu Group Ltd. | Charge sharing in a TCAM array |
CN101714401B (zh) * | 2009-11-06 | 2013-01-02 | 东南大学 | 用以增强存储单元阵列容量和密度的亚阈值敏感放大电路 |
KR20130136343A (ko) * | 2012-06-04 | 2013-12-12 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 동작 방법 |
CN104578015A (zh) * | 2013-10-17 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | 抑制高压瞬态电流的位线电路 |
EP3633678A4 (en) * | 2017-06-23 | 2020-04-29 | Huawei Technologies Co. Ltd. | STORAGE AND DATA WRITING |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4890263A (en) * | 1988-05-31 | 1989-12-26 | Dallas Semiconductor Corporation | RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines |
KR100208142B1 (ko) * | 1990-09-26 | 1999-07-15 | 가나이 쓰도무 | 반도체 메모리 |
CN1202530C (zh) * | 1998-04-01 | 2005-05-18 | 三菱电机株式会社 | 在低电源电压下高速动作的静态型半导体存储装置 |
JP2000268576A (ja) * | 1999-03-16 | 2000-09-29 | Toshiba Microelectronics Corp | 半導体記憶装置 |
US6275415B1 (en) * | 1999-10-12 | 2001-08-14 | Advanced Micro Devices, Inc. | Multiple byte channel hot electron programming using ramped gate and source bias voltage |
US6366512B1 (en) * | 2000-11-30 | 2002-04-02 | Global Unichip Corporation | Error write protection circuit used in semiconductor memory device |
JP2003016785A (ja) * | 2001-06-28 | 2003-01-17 | Sharp Corp | 半導体記憶装置およびそれを用いた情報機器 |
JP4007823B2 (ja) * | 2002-02-21 | 2007-11-14 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
JP4162076B2 (ja) * | 2002-05-30 | 2008-10-08 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
-
2003
- 2003-07-31 CN CN03820748.6A patent/CN1679111B/zh not_active Expired - Fee Related
- 2003-07-31 WO PCT/IB2003/003729 patent/WO2004021353A1/en active Application Filing
- 2003-07-31 JP JP2004532414A patent/JP4262678B2/ja not_active Expired - Fee Related
- 2003-07-31 US US10/525,662 patent/US7474553B2/en not_active Expired - Lifetime
- 2003-07-31 EP EP03791128A patent/EP1537583A1/en not_active Withdrawn
- 2003-07-31 AU AU2003253205A patent/AU2003253205A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014139860A (ja) * | 2014-03-28 | 2014-07-31 | Renesas Electronics Corp | 半導体集積回路装置 |
Also Published As
Publication number | Publication date |
---|---|
EP1537583A1 (en) | 2005-06-08 |
US20050254315A1 (en) | 2005-11-17 |
US7474553B2 (en) | 2009-01-06 |
WO2004021353A1 (en) | 2004-03-11 |
JP4262678B2 (ja) | 2009-05-13 |
CN1679111B (zh) | 2011-06-15 |
AU2003253205A1 (en) | 2004-03-19 |
CN1679111A (zh) | 2005-10-05 |
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