JP4787638B2 - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
- Publication number
- JP4787638B2 JP4787638B2 JP2006073339A JP2006073339A JP4787638B2 JP 4787638 B2 JP4787638 B2 JP 4787638B2 JP 2006073339 A JP2006073339 A JP 2006073339A JP 2006073339 A JP2006073339 A JP 2006073339A JP 4787638 B2 JP4787638 B2 JP 4787638B2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer wiring
- substrate
- wiring board
- region
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4635—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating flexible circuit boards using additional insulating adhesive materials between the boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/05—Flexible printed circuits [FPCs]
- H05K2201/055—Folded back on itself
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Description
図1は、本発明の第1の実施の形態に係る多層配線基板の断面図であり、図2は、電子部品及び実装基板と接続された多層配線基板の断面図である。図2において、図1に示す多層配線基板10と同一構成部分には同一符号を付す。
図23は、本発明の第2の実施の形態に係る多層配線基板の断面図である。図23において、第1の実施の形態の多層配線基板10と同一構成部分には同一符号を付す。
11,131 第1の配線基板
12,132 第2の配線基板
13 アンダーフィル樹脂
14,54,101,134,135,138 基板
14A,54A,101A,134A,135A,138A 上面
14B,54B,101B,134B,135B,138B 下面
15,55 貫通ビア
16 第1の多層配線構造体
17,57 内部接続端子
21,61 第1構造体
22,62 第2構造体
23,63 貫通孔
25,65 ビア部
26,27,66,67 配線部
29,41,69,81,102,103 絶縁層
29A,33A,41A,43A,69A,73A,81A,83A,108A,108B,109A,109B 開口部
29B,41B,69B,81B,102A,103A 面
31,42,71,82 配線パターン
33,43,73,83,114,115 ソルダーレジスト
35,45,75,85 拡散防止膜
37,47,77,87 ビア
38,48,78,88 配線
56 第2の多層配線構造体
91,92 外部接続端子
95 電子部品
96,99 パッド
98 実装基板
105,106 シード層
108,109 レジスト膜
117 マスキング材
118 はんだ
120,145 構造体
121 第1の溝部
122 第2の溝部
A1,A2 第1の領域
B1,B2 第2の領域
C1,C2 第3の領域
D1〜D3 距離
E,G 切断位置
M1〜M6 厚さ
W1,W2 幅
Claims (4)
- 複数の絶縁層及び配線パターンを備えた第1の多層配線構造体が形成される第1の領域と、該第1の領域から離間した位置に設けられ、複数の絶縁層及び配線パターンを備えた第2の多層配線構造体が形成される第2の領域とを有する基板を準備する基板準備工程と、
前記基板の前記第1及び第2の領域に、それぞれ前記第1の多層配線構造体と前記第2の多層配線構造体とを同時に形成する第1及び第2の多層配線構造体形成工程と、
前記第1の多層配線構造体と第2の多層配線構造体とが対向するように、前記基板を折り曲げて、前記第1の多層配線構造体と前記第2の多層配線構造体とを電気的に接続する接続工程と、
前記折り曲げられた部分の基板から前記第1及び第2の領域に対応する前記基板が分離するように、前記基板を切断する基板切断工程と、を含むことを特徴とする配線基板の製造方法。 - 前記基板切断工程よりも前に、前記第1の領域に対応する前記基板と前記第2の領域に対応する前記基板との間に位置する前記基板に、溝部を形成する溝部形成工程を設けたことを特徴とする請求項1記載の配線基板の製造方法。
- 前記溝部は、前記基板を貫通するように形成することを特徴とする請求項2記載の配線基板の製造方法。
- 前記溝部は、第1の溝部と、第2の溝部とを有し、
前記第1の溝部は、前記第1の領域の近傍に形成し、
前記第2の溝部は、前記第2の領域の近傍に形成することを特徴とする請求項2または3記載の配線基板の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006073339A JP4787638B2 (ja) | 2006-03-16 | 2006-03-16 | 配線基板の製造方法 |
US11/724,265 US7772109B2 (en) | 2006-03-16 | 2007-03-15 | Manufacturing method of multilayer wiring substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006073339A JP4787638B2 (ja) | 2006-03-16 | 2006-03-16 | 配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007250900A JP2007250900A (ja) | 2007-09-27 |
JP4787638B2 true JP4787638B2 (ja) | 2011-10-05 |
Family
ID=38518376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006073339A Expired - Fee Related JP4787638B2 (ja) | 2006-03-16 | 2006-03-16 | 配線基板の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7772109B2 (ja) |
JP (1) | JP4787638B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102256453B (zh) * | 2010-05-21 | 2013-12-25 | 富葵精密组件(深圳)有限公司 | 多层电路板制作方法 |
KR101786512B1 (ko) * | 2010-07-26 | 2017-10-18 | 엘지전자 주식회사 | 다층 연성회로기판의 제조방법 |
KR101326999B1 (ko) * | 2012-03-07 | 2013-11-13 | 엘지이노텍 주식회사 | 인쇄회로기판 및 그의 제조 방법 |
CN105899003B (zh) | 2015-11-06 | 2019-11-26 | 武汉光谷创元电子有限公司 | 单层电路板、多层电路板以及它们的制造方法 |
CN109803481B (zh) * | 2017-11-17 | 2021-07-06 | 英业达科技有限公司 | 多层印刷电路板及制作多层印刷电路板的方法 |
TWI706706B (zh) * | 2019-06-26 | 2020-10-01 | 南亞電路板股份有限公司 | 電路板結構及其製造方法 |
CN112312682B (zh) * | 2019-07-30 | 2023-07-21 | 宏启胜精密电子(秦皇岛)有限公司 | 具有厚铜线路的电路板及其制作方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0997956A (ja) * | 1995-09-29 | 1997-04-08 | Nec Kansai Ltd | プリント基板 |
JPH09283931A (ja) | 1996-04-17 | 1997-10-31 | Shinko Electric Ind Co Ltd | 多層配線基板 |
JPH1022590A (ja) * | 1996-07-08 | 1998-01-23 | Oki Electric Ind Co Ltd | 多面取りプリント配線基板 |
JPH10270829A (ja) * | 1997-03-28 | 1998-10-09 | Hitachi Chem Co Ltd | 配線板の製造方法 |
JPH1184355A (ja) * | 1997-09-11 | 1999-03-26 | Hitachi Ltd | 液晶表示装置 |
JP2001320171A (ja) * | 2000-05-08 | 2001-11-16 | Shinko Electric Ind Co Ltd | 多層配線基板及び半導体装置 |
JP2003017851A (ja) * | 2001-06-29 | 2003-01-17 | Murata Mfg Co Ltd | 多層セラミック基板の製造方法 |
FI118991B (fi) * | 2004-02-09 | 2008-06-13 | Upstream Engineering Oy | Menetelmä kolmiulotteisten optisten komponenttien valmistamiseksi |
JP4123206B2 (ja) * | 2004-08-31 | 2008-07-23 | ソニー株式会社 | 多層配線板及び多層配線板の製造方法 |
-
2006
- 2006-03-16 JP JP2006073339A patent/JP4787638B2/ja not_active Expired - Fee Related
-
2007
- 2007-03-15 US US11/724,265 patent/US7772109B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20070218589A1 (en) | 2007-09-20 |
US7772109B2 (en) | 2010-08-10 |
JP2007250900A (ja) | 2007-09-27 |
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