JP4775993B2 - 半導体素子封止剤、半導体装置および半導体装置の実装方法 - Google Patents

半導体素子封止剤、半導体装置および半導体装置の実装方法 Download PDF

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Publication number
JP4775993B2
JP4775993B2 JP2004105620A JP2004105620A JP4775993B2 JP 4775993 B2 JP4775993 B2 JP 4775993B2 JP 2004105620 A JP2004105620 A JP 2004105620A JP 2004105620 A JP2004105620 A JP 2004105620A JP 4775993 B2 JP4775993 B2 JP 4775993B2
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Japan
Prior art keywords
semiconductor element
semiconductor device
component
group
weight
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Expired - Fee Related
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JP2004105620A
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English (en)
Japanese (ja)
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JP2005294437A5 (enExample
JP2005294437A (ja
Inventor
実 一色
博司 江南
好次 森田
勝利 峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DuPont Toray Specialty Materials KK
Original Assignee
Dow Corning Toray Co Ltd
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Publication date
Application filed by Dow Corning Toray Co Ltd filed Critical Dow Corning Toray Co Ltd
Priority to JP2004105620A priority Critical patent/JP4775993B2/ja
Publication of JP2005294437A publication Critical patent/JP2005294437A/ja
Publication of JP2005294437A5 publication Critical patent/JP2005294437A5/ja
Application granted granted Critical
Publication of JP4775993B2 publication Critical patent/JP4775993B2/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Compositions Of Macromolecular Compounds (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2004105620A 2004-03-31 2004-03-31 半導体素子封止剤、半導体装置および半導体装置の実装方法 Expired - Fee Related JP4775993B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004105620A JP4775993B2 (ja) 2004-03-31 2004-03-31 半導体素子封止剤、半導体装置および半導体装置の実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004105620A JP4775993B2 (ja) 2004-03-31 2004-03-31 半導体素子封止剤、半導体装置および半導体装置の実装方法

Publications (3)

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JP2005294437A JP2005294437A (ja) 2005-10-20
JP2005294437A5 JP2005294437A5 (enExample) 2007-05-24
JP4775993B2 true JP4775993B2 (ja) 2011-09-21

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JP2004105620A Expired - Fee Related JP4775993B2 (ja) 2004-03-31 2004-03-31 半導体素子封止剤、半導体装置および半導体装置の実装方法

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5259947B2 (ja) * 2006-11-24 2013-08-07 モメンティブ・パフォーマンス・マテリアルズ・ジャパン合同会社 半導体封止用シリコーン組成物および半導体装置
JP5014774B2 (ja) * 2006-12-26 2012-08-29 モメンティブ・パフォーマンス・マテリアルズ・ジャパン合同会社 付加反応硬化型シリコーン組成物および半導体装置
JP5552958B2 (ja) * 2010-08-17 2014-07-16 Tdk株式会社 端子構造、プリント配線板、モジュール基板及び電子デバイス
JP6524879B2 (ja) * 2015-10-13 2019-06-05 信越化学工業株式会社 付加一液硬化型熱伝導性シリコーングリース組成物
JP2021075655A (ja) * 2019-11-12 2021-05-20 信越化学工業株式会社 導電性シリコーン組成物、導電性シリコーン硬化物、導電性シリコーン硬化物の製造方法、及び導電性シリコーン積層体
US20240002605A1 (en) * 2020-06-30 2024-01-04 Dow Toray Co., Ltd. Curable organopolysiloxane composition and use therefor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3207929B2 (ja) * 1992-07-16 2001-09-10 東レ・ダウコーニング・シリコーン株式会社 半導体素子被覆剤および半導体装置
JPH11199677A (ja) * 1997-11-12 1999-07-27 Kanegafuchi Chem Ind Co Ltd 硬化性組成物及びそれを用いた成形体の作製方法
JP2001089662A (ja) * 1999-09-22 2001-04-03 Kanegafuchi Chem Ind Co Ltd 硬化性組成物及びそれを用いた成形体の作製方法
JP4889867B2 (ja) * 2001-03-13 2012-03-07 株式会社カネカ 末端にアルケニル基を有するビニル系重合体の製造方法、ビニル系重合体および硬化性組成物
JP3865639B2 (ja) * 2002-01-28 2007-01-10 信越化学工業株式会社 半導体封止用シリコーン組成物および半導体装置

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