JP4758439B2 - 半導体デバイスを試験する方法及びシステム - Google Patents
半導体デバイスを試験する方法及びシステム Download PDFInfo
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- JP4758439B2 JP4758439B2 JP2007548324A JP2007548324A JP4758439B2 JP 4758439 B2 JP4758439 B2 JP 4758439B2 JP 2007548324 A JP2007548324 A JP 2007548324A JP 2007548324 A JP2007548324 A JP 2007548324A JP 4758439 B2 JP4758439 B2 JP 4758439B2
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- 238000012360 testing method Methods 0.000 title claims description 426
- 239000004065 semiconductor Substances 0.000 title claims description 63
- 238000000034 method Methods 0.000 title claims description 11
- 230000004044 response Effects 0.000 claims description 30
- 238000012986 modification Methods 0.000 claims description 6
- 230000004048 modification Effects 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 85
- 230000006870 function Effects 0.000 description 16
- 238000012544 monitoring process Methods 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000013598 vector Substances 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31924—Voltage or current aspects, e.g. driver, receiver
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Description
Claims (19)
- 複数の試験信号であって、該試験信号の少なくとも2つは異なる電流レベルを有する複数の試験信号の1つを含むDC試験信号を提供するように構成されたPMU段と、
AC試験信号を生成するように構成されたPE段と、
第1のモードにおいて、前記DC試験信号が、前記複数の試験信号の内他の信号よりも高い電流レベルを有する試験信号を生成する場合、前記DC試験信号の変形を提供するように構成され、第2のモードにおいて、前記AC試験信号の変形を提供するように構成されるドライバ回路と、
半導体デバイスへの経路に向かって試験信号が通過する出力段と、を備え、
前記DC試験信号が前記高い電流レベルより低い電流レベルを有する試験信号を生成する場合、該DC試験信号は前記ドライバ回路をバイパスする回路を介して前記出力段に回る、
半導体デバイス試験装置。 - 前記出力段はインピーダンス回路からなる、請求項1に記載の半導体デバイス試験装置。
- 前記ドライバ回路によって提供される前記DC試験信号の変形は、前記PMU段によって提供される前記DC試験信号の増幅された変形である、請求項1に記載の半導体デバイス試験装置。
- 前記ドライバ回路によって提供される前記AC試験信号の変形は、前記PE段によって生成される前記AC試験信号の増幅された変形である、請求項1に記載の半導体デバイス試験装置。
- 前記ドライバをバイパスする回路は、前記DC試験信号が前記出力段に通過するスイッチを含む、請求項2に記載の半導体デバイス試験装置。
- 前記出力段は抵抗を含む、請求項1に記載の半導体デバイス試験装置。
- 前記DC試験信号は、約50ミリアンペアの電流を有する、請求項1に記載の半導体デバイス試験装置。
- 複数の試験信号であって、該試験信号の各々は、他の試験信号と異なる電流レベルを有する複数の試験信号の1つを含むDC試験信号を提供するように構成されたPMU段と、
AC試験信号を生成するように構成されたPE段と、
制御信号に応答して、
(i)前記DC試験信号が、前記複数の試験信号の内他の信号よりも高い電流レベルを有する試験信号を生成する場合、前記DC試験信号の変形、
(ii)前記AC試験信号の変形、
のいずれかを通過させるように構成される回路と、
試験信号が通過する出力段と、を備え、
前記DC試験信号が前記高い電流レベルより低い電流レベルを有する試験信号を生成する場合、該DC試験信号は前記回路をバイパスする回路を介して前記出力段に回る、
半導体デバイス試験装置。 - 前記回路は、信号増幅を行うように構成されるドライバ回路を含む、請求項8に記載の半導体デバイス試験装置。
- 前記回路は、DC試験信号を前記出力段に提供するように構成されるスイッチを含む、請求項8に記載の半導体デバイス試験装置。
- 前記出力段は抵抗を含む、請求項8に記載の半導体デバイス試験装置。
- 前記PMU段、前記PE段、前記回路、および前記出力段は、集積回路からなる、請求項8に記載の半導体デバイス試験装置。
- 前記AC試験信号の変形は前記PE段によって生成されるAC試験信号の増幅された変形からなり、前記DC試験信号の変形は前記PMU段によって提供されるDC試験信号の増幅された変形からなる、請求項8に記載の半導体デバイス試験装置。
- 前記DC試験信号の前記増幅された変形は、前記複数の試験信号の内他の信号よりも高い電流を有する、請求項8に記載の半導体デバイス試験装置。
- 前記出力段は50オーム抵抗を含む、請求項13に記載の半導体デバイス試験装置。
- 半導体デバイスに試験信号を提供する方法であって、
PMU段を用いてDC試験信号を生成し、
前記DC試験信号が、所定の電流レベルより高い電流レベルを有するDC試験信号を生成する場合、PE段からのAC信号を増幅するようにも構成されたドライバ回路を用いて前記DC試験信号を増幅し、
前記DC試験信号が前記所定の電流レベルより低い電流レベルを有する場合、前記DC試験信号が前記ドライバ回路をバイパスし、
前記DC試験信号または増幅されたDC試験信号を被試験半導体デバイスに出力段を介して送出する、ことを含み、
前記出力段は、増幅されたAC試験信号を前記PE段から前記半導体デバイスに提供するようにも構成される、方法。 - 前記出力段を介して前記増幅されたDC試験信号を送出することは、抵抗を介して増幅されたDC試験信号を送ることを含む、請求項16に記載の方法。
- 前記DC試験信号が前記ドライバ回路をバイパスするようにすることは、前記DC試験信号をスイッチに通すことを含む、請求項16に記載の方法。
- 前記DC試験信号を前記スイッチに通すことは、前記スイッチを閉位置にすることを含む、請求項18に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/018,540 | 2004-12-21 | ||
US11/018,540 US7256600B2 (en) | 2004-12-21 | 2004-12-21 | Method and system for testing semiconductor devices |
PCT/US2005/045605 WO2006068936A2 (en) | 2004-12-21 | 2005-12-16 | A method and system for testing semiconductor devices |
Publications (2)
Publication Number | Publication Date |
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JP2008524629A JP2008524629A (ja) | 2008-07-10 |
JP4758439B2 true JP4758439B2 (ja) | 2011-08-31 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2007548324A Active JP4758439B2 (ja) | 2004-12-21 | 2005-12-16 | 半導体デバイスを試験する方法及びシステム |
Country Status (6)
Country | Link |
---|---|
US (1) | US7256600B2 (ja) |
EP (1) | EP1828789A2 (ja) |
JP (1) | JP4758439B2 (ja) |
KR (1) | KR100904673B1 (ja) |
CN (1) | CN101084445A (ja) |
WO (1) | WO2006068936A2 (ja) |
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- 2005-12-16 CN CNA2005800439253A patent/CN101084445A/zh active Pending
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- 2005-12-16 WO PCT/US2005/045605 patent/WO2006068936A2/en active Search and Examination
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Also Published As
Publication number | Publication date |
---|---|
KR20070073982A (ko) | 2007-07-10 |
CN101084445A (zh) | 2007-12-05 |
US20060132165A1 (en) | 2006-06-22 |
EP1828789A2 (en) | 2007-09-05 |
US7256600B2 (en) | 2007-08-14 |
WO2006068936A3 (en) | 2006-09-08 |
KR100904673B1 (ko) | 2009-06-25 |
JP2008524629A (ja) | 2008-07-10 |
WO2006068936A2 (en) | 2006-06-29 |
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