JP4739213B2 - ボンディング層が消滅する間接ボンディング - Google Patents
ボンディング層が消滅する間接ボンディング Download PDFInfo
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- JP4739213B2 JP4739213B2 JP2006530756A JP2006530756A JP4739213B2 JP 4739213 B2 JP4739213 B2 JP 4739213B2 JP 2006530756 A JP2006530756 A JP 2006530756A JP 2006530756 A JP2006530756 A JP 2006530756A JP 4739213 B2 JP4739213 B2 JP 4739213B2
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- 239000010410 layer Substances 0.000 claims description 396
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 137
- 239000000758 substrate Substances 0.000 claims description 105
- 238000000034 method Methods 0.000 claims description 90
- 229910052732 germanium Inorganic materials 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 38
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 37
- 235000012431 wafers Nutrition 0.000 claims description 29
- 238000009792 diffusion process Methods 0.000 claims description 26
- 238000004140 cleaning Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 239000013626 chemical specie Substances 0.000 claims description 2
- 238000002156 mixing Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 34
- 229910052710 silicon Inorganic materials 0.000 description 34
- 239000010703 silicon Substances 0.000 description 34
- 238000007254 oxidation reaction Methods 0.000 description 21
- 230000003647 oxidation Effects 0.000 description 19
- 229910004298 SiO 2 Inorganic materials 0.000 description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 11
- 230000036961 partial effect Effects 0.000 description 6
- 238000011282 treatment Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 230000000670 limiting effect Effects 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 238000004381 surface treatment Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 150000002290 germanium Chemical class 0.000 description 2
- 230000002209 hydrophobic effect Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- VYQRBKCKQCRYEE-UHFFFAOYSA-N ctk1a7239 Chemical compound C12=CC=CC=C2N2CC=CC3=NC=CC1=C32 VYQRBKCKQCRYEE-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
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Description
Claims (18)
- 支持基板上に半導体材料の薄層を備える構造を製造する方法であって、支持基板と緩和された半導体材料の上部層を備えるドナー基板とをボンディングすることによって前記薄層が得られ、前記方法が、
前記緩和された上部層の前記材料の元素の拡散を受ける歪みボンディング層を前記緩和された上部層上に形成する工程と、
そのボンディング接着を確実に行うために前記歪みボンディング層を洗浄する工程と、
あらかじめ前記緩和された上部層上に形成されかつ洗浄された前記歪みボンディング層の側から、前記支持基板上に前記ドナー基板を接着する工程と、
前記緩和された上部層から前記元素を前記歪みボンディング層中に拡散して、前記歪みボンディング層及び前記緩和された上部層中における前記元素の濃度を均一化し、前記歪みボンディング層及び前記緩和された上部層を用いて前記構造の前記薄層を構成する工程と、
を備えることを特徴とする方法。 - 前記緩和された上部層から前記歪みボンディング層中に前記元素を拡散する工程中に、前記歪みボンディング層が前記緩和された上部層中に混合して前記構造の前記薄層を形成することにより、前記歪みボンディング層が消滅することを特徴とする、請求項1に記載の方法。
- ボンディングに続いて、そして、拡散に先立って、前記ドナー基板の一部分を除去して、前記緩和された上部層の一部分だけを保持して、前記支持基板と、前記歪みボンディング層と、前記歪みボンディング層と一体になって残存する前記緩和された上部層の残りによって形成される薄層とを備える中間構造を得ることを目指した薄層化工程をさらに備えることを特徴とする、請求項2に記載の方法。
- 前記緩和された上部層の層中にボンディングに先立って形成される脆弱ゾーンにおける前記ドナー基板からの剥離によって薄層化が実行されることを特徴とする、請求項3に記載の方法。
- 前記緩和された上部層中に化学種を注入することによって前記脆弱ゾーンが形成されることを特徴とする、請求項4に記載の方法。
- 注入に先立って、前記歪みボンディング層上に保護層を堆積させることを目指した工程を備え、前記ボンディング工程の前に前記保護層が除去されることを特徴とする、請求項5に記載の方法。
- 前記薄層化工程が少なくとも1つのエッチング工程を備えることを特徴とする、請求項3から6のいずれか一項に記載の方法。
- 薄層化の後に得られる前記中間構造に対して熱処理を加えることにより前記拡散工程が実行されることを特徴とする、請求項3から7のいずれか一項に記載の方法。
- 薄層化の後に得られる前記構造のボンディング境界面を安定化させるための熱処理中に前記拡散工程が実行されることを特徴とする、請求項8に記載の方法。
- 前記熱処理が1000°Cと1100°Cの間で2時間実行されることを特徴とする、請求項8又は9に記載の方法。
- 前記緩和された上部層がシリコン−ゲルマニウムSiGeから形成され、前記拡散工程が前記緩和された上部層から前記歪みボンディング層中に前記元素Geを拡散することを特徴とする、請求項1から10のいずれか一項に記載の方法。
- 酸化物層に対して前記堆積させられたSiGe膜のボンディングが確実に行われるように、前記歪みボンディング層を形成する前記工程が、緩和されたSiGeの膜を前記緩和されたSiGe上部層上に堆積させる工程を備えることを特徴とする、請求項11に記載の方法。
- 前記堆積させられ緩和されたSiGe膜中の前記ゲルマニウムの濃度が20%未満であることを特徴とする、請求項12に記載の方法。
- 酸化された支持基板に対して直接にボンディングが実行されて、良好な品質のSiGe/酸化膜結合を実現することを特徴とする、請求項12又は13に記載の方法。
- 前記緩和されたSiGe上部層と前記歪みボンディング層の同化作用によって均一な濃度のゲルマニウムを有する層が得られるように、前記拡散工程中に、前記元素Geが前記歪みボンディング層中に拡散することを特徴とする、請求項14に記載の方法。
- 前記SiGeボンディング層の前記洗浄がRCAタイプの処理に従って実施されることを特徴とする、請求項12から15のいずれか一項に記載の方法。
- 前記洗浄工程が前記歪みボンディング層に接着すべき前記支持基板の面の洗浄工程も備えることを特徴とする、請求項1から16のいずれか一項に記載の方法。
- 半導体材料の第1のウェーハと第2のウェーハとを共に接着する方法であって、前記第1のウェーハが緩和された上部層を備え、前記第2のウェーハが自由面を備え、前記方法が、
前記第1のウェーハの前記緩和された上部層上に、前記緩和された上部層の前記材料の元素の拡散を受ける歪みボンディング層を形成する工程と、
そのボンディング接着を確実に行うために前記歪みボンディング層を洗浄する工程と、
あらかじめ前記緩和された上部層上に形成されかつ洗浄された前記歪みボンディング層の側から、前記支持基板に対して前記ドナー基板を接着する工程と、
前記ウェーハが共に接着され、前記第1のウェーハの前記緩和された上部層が前記第2のウェーハの前記自由面に結合されるように、前記緩和された上部層の前記元素を前記歪みボンディング層中に拡散させて前記歪みボンディング層及び前記緩和された上部層中における前記元素の濃度を均一化させ、そして、前記歪みボンディング層を前記緩和された上部層との混合によって消滅させる工程と、
を備えることを特徴とする方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0311418A FR2860340B1 (fr) | 2003-09-30 | 2003-09-30 | Collage indirect avec disparition de la couche de collage |
FR03/11418 | 2003-09-30 | ||
PCT/IB2004/003324 WO2005031852A1 (en) | 2003-09-30 | 2004-09-30 | Indirect bonding with disappearance of the bonding layer |
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JP2011005104A Division JP2011109125A (ja) | 2003-09-30 | 2011-01-13 | ボンディング層が消滅する間接ボンディング |
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JP2007507874A JP2007507874A (ja) | 2007-03-29 |
JP4739213B2 true JP4739213B2 (ja) | 2011-08-03 |
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JP2011005104A Withdrawn JP2011109125A (ja) | 2003-09-30 | 2011-01-13 | ボンディング層が消滅する間接ボンディング |
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US (1) | US7078353B2 (ja) |
EP (1) | EP1668693A1 (ja) |
JP (2) | JP4739213B2 (ja) |
KR (1) | KR100834200B1 (ja) |
CN (1) | CN100590838C (ja) |
FR (1) | FR2860340B1 (ja) |
WO (1) | WO2005031852A1 (ja) |
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FR2912550A1 (fr) * | 2007-02-14 | 2008-08-15 | Soitec Silicon On Insulator | Procede de fabrication d'une structure ssoi. |
FR2912841B1 (fr) * | 2007-02-15 | 2009-05-22 | Soitec Silicon On Insulator | Procede de polissage d'heterostructures |
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FR2932108B1 (fr) | 2008-06-10 | 2019-07-05 | Soitec | Polissage de couches de germanium |
FR2951869A1 (fr) * | 2009-10-26 | 2011-04-29 | Commissariat Energie Atomique | Procede de realisation d'une structure a couche enterree par implantation et transfert |
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US6841457B2 (en) * | 2002-07-16 | 2005-01-11 | International Business Machines Corporation | Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion |
US20040192067A1 (en) * | 2003-02-28 | 2004-09-30 | Bruno Ghyselen | Method for forming a relaxed or pseudo-relaxed useful layer on a substrate |
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2003
- 2003-09-30 FR FR0311418A patent/FR2860340B1/fr not_active Expired - Fee Related
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2004
- 2004-01-06 US US10/753,173 patent/US7078353B2/en not_active Expired - Fee Related
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- 2004-09-30 WO PCT/IB2004/003324 patent/WO2005031852A1/en active Application Filing
- 2004-09-30 EP EP04769613A patent/EP1668693A1/en not_active Withdrawn
- 2004-09-30 CN CN200480028279A patent/CN100590838C/zh not_active Expired - Fee Related
- 2004-09-30 KR KR1020067004222A patent/KR100834200B1/ko not_active IP Right Cessation
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JP2002305293A (ja) * | 2001-04-06 | 2002-10-18 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
JP2003031495A (ja) * | 2001-07-12 | 2003-01-31 | Hitachi Ltd | 半導体装置用基板の製造方法および半導体装置の製造方法 |
JP2003168789A (ja) * | 2001-11-29 | 2003-06-13 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
Also Published As
Publication number | Publication date |
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EP1668693A1 (en) | 2006-06-14 |
JP2007507874A (ja) | 2007-03-29 |
CN1860604A (zh) | 2006-11-08 |
JP2011109125A (ja) | 2011-06-02 |
US7078353B2 (en) | 2006-07-18 |
FR2860340A1 (fr) | 2005-04-01 |
FR2860340B1 (fr) | 2006-01-27 |
WO2005031852A1 (en) | 2005-04-07 |
US20050070078A1 (en) | 2005-03-31 |
CN100590838C (zh) | 2010-02-17 |
KR20060064061A (ko) | 2006-06-12 |
KR100834200B1 (ko) | 2008-05-30 |
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