JP4737929B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4737929B2
JP4737929B2 JP2003414596A JP2003414596A JP4737929B2 JP 4737929 B2 JP4737929 B2 JP 4737929B2 JP 2003414596 A JP2003414596 A JP 2003414596A JP 2003414596 A JP2003414596 A JP 2003414596A JP 4737929 B2 JP4737929 B2 JP 4737929B2
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JP
Japan
Prior art keywords
data
input
test
output
circuit
Prior art date
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Expired - Lifetime
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JP2003414596A
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English (en)
Japanese (ja)
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JP2005174486A5 (enExample
JP2005174486A (ja
Inventor
良 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2003414596A priority Critical patent/JP4737929B2/ja
Priority to US11/008,270 priority patent/US7406637B2/en
Publication of JP2005174486A publication Critical patent/JP2005174486A/ja
Publication of JP2005174486A5 publication Critical patent/JP2005174486A5/ja
Application granted granted Critical
Publication of JP4737929B2 publication Critical patent/JP4737929B2/ja
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Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G11C2029/3602—Pattern generator

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  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2003414596A 2003-12-12 2003-12-12 半導体記憶装置 Expired - Lifetime JP4737929B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003414596A JP4737929B2 (ja) 2003-12-12 2003-12-12 半導体記憶装置
US11/008,270 US7406637B2 (en) 2003-12-12 2004-12-10 Semiconductor memory device capable of testing memory cells at high speed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003414596A JP4737929B2 (ja) 2003-12-12 2003-12-12 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2005174486A JP2005174486A (ja) 2005-06-30
JP2005174486A5 JP2005174486A5 (enExample) 2006-12-28
JP4737929B2 true JP4737929B2 (ja) 2011-08-03

Family

ID=34734340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003414596A Expired - Lifetime JP4737929B2 (ja) 2003-12-12 2003-12-12 半導体記憶装置

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US (1) US7406637B2 (enExample)
JP (1) JP4737929B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8286046B2 (en) 2001-09-28 2012-10-09 Rambus Inc. Integrated circuit testing module including signal shaping interface
US8166361B2 (en) 2001-09-28 2012-04-24 Rambus Inc. Integrated circuit testing module configured for set-up and hold time testing
JP5068739B2 (ja) * 2005-03-18 2012-11-07 ラムバス・インコーポレーテッド 集積回路試験モジュール
KR100843197B1 (ko) * 2006-02-28 2008-07-02 삼성전자주식회사 위상이 다른 다수개의 드라우지 클럭 신호들을 내부적으로발생하는 집적회로 장치
US7362633B2 (en) * 2006-03-21 2008-04-22 Infineon Technologies Ag Parallel read for front end compression mode
JP2007272982A (ja) * 2006-03-31 2007-10-18 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその検査方法
KR100859833B1 (ko) * 2006-07-20 2008-09-23 주식회사 하이닉스반도체 반도체 메모리 장치
JP2008077763A (ja) * 2006-09-21 2008-04-03 Toshiba Corp 半導体記憶装置
JP2008165887A (ja) * 2006-12-27 2008-07-17 Rohm Co Ltd メモリリード回路、それを用いたメモリ装置
KR20130015725A (ko) * 2011-08-04 2013-02-14 에스케이하이닉스 주식회사 반도체 메모리 장치를 포함하는 시스템-인 패키지 및 시스템-인 패키지의 입출력 핀 확인방법
US10236042B2 (en) 2016-10-28 2019-03-19 Integrated Silicon Solution, Inc. Clocked commands timing adjustments method in synchronous semiconductor integrated circuits
US10068626B2 (en) 2016-10-28 2018-09-04 Integrated Silicon Solution, Inc. Clocked commands timing adjustments in synchronous semiconductor integrated circuits

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695440B2 (ja) * 1988-06-01 1994-11-24 三菱電機株式会社 メモリテスト装置のメモリパターン発生器
JPH0371500A (ja) * 1989-08-11 1991-03-27 Sony Corp 半導体メモリ
JP2761559B2 (ja) * 1989-11-13 1998-06-04 株式会社アドバンテスト 半導体メモリ試験用データ発生装置
JPH05256919A (ja) * 1992-03-13 1993-10-08 Fujitsu Ltd 半導体記憶装置
JP3061988B2 (ja) * 1993-09-07 2000-07-10 日本電気株式会社 高速自己テスト回路内蔵半導体記憶装置
US5668815A (en) * 1996-08-14 1997-09-16 Advanced Micro Devices, Inc. Method for testing integrated memory using an integrated DMA controller
US6661839B1 (en) * 1998-03-24 2003-12-09 Advantest Corporation Method and device for compressing and expanding data pattern
JPH11329000A (ja) 1998-05-19 1999-11-30 Mitsubishi Electric Corp 内蔵メモリテスト方法、およびそれに用いるバスインタフェースユニット、コマンドデコーダ
JP4601737B2 (ja) * 1998-10-28 2010-12-22 株式会社東芝 メモリ混載ロジックｌｓｉ
JP2000207900A (ja) * 1999-01-12 2000-07-28 Mitsubishi Electric Corp 同期型半導体記憶装置
JP3667146B2 (ja) * 1999-03-30 2005-07-06 台湾積體電路製造股▲ふん▼有限公司 メモリ用内蔵自己テスト回路
JP3576457B2 (ja) * 1999-05-11 2004-10-13 シャープ株式会社 １チップマイクロコンピュータおよびその制御方法、ならびにそれを用いたｉｃカード
US6591385B1 (en) * 2000-09-11 2003-07-08 Agilent Technologies, Inc. Method and apparatus for inserting programmable latency between address and data information in a memory tester
US6851076B1 (en) * 2000-09-28 2005-02-01 Agilent Technologies, Inc. Memory tester has memory sets configurable for use as error catch RAM, Tag RAM's, buffer memories and stimulus log RAM
US20020133769A1 (en) * 2001-03-15 2002-09-19 Cowles Timothy B. Circuit and method for test and repair
DE10115880B4 (de) * 2001-03-30 2007-01-25 Infineon Technologies Ag Testschaltung zum kritischen Testen einer synchronen Speicherschaltung
US6834364B2 (en) * 2001-04-19 2004-12-21 Agilent Technologies, Inc. Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences
US6779140B2 (en) * 2001-06-29 2004-08-17 Agilent Technologies, Inc. Algorithmically programmable memory tester with test sites operating in a slave mode
JP2003068098A (ja) * 2001-08-28 2003-03-07 Mitsubishi Electric Corp テスト回路装置および半導体集積回路装置

Also Published As

Publication number Publication date
US20050152190A1 (en) 2005-07-14
JP2005174486A (ja) 2005-06-30
US7406637B2 (en) 2008-07-29

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