JP4732131B2 - 同期回路システム - Google Patents

同期回路システム Download PDF

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Publication number
JP4732131B2
JP4732131B2 JP2005321682A JP2005321682A JP4732131B2 JP 4732131 B2 JP4732131 B2 JP 4732131B2 JP 2005321682 A JP2005321682 A JP 2005321682A JP 2005321682 A JP2005321682 A JP 2005321682A JP 4732131 B2 JP4732131 B2 JP 4732131B2
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Japan
Prior art keywords
output
buffer
timing
circuit
shows
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Expired - Fee Related
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JP2005321682A
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Japanese (ja)
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JP2007129601A (ja
JP2007129601A5 (https=
Inventor
正則 菊池
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2005321682A priority Critical patent/JP4732131B2/ja
Publication of JP2007129601A publication Critical patent/JP2007129601A/ja
Publication of JP2007129601A5 publication Critical patent/JP2007129601A5/ja
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Publication of JP4732131B2 publication Critical patent/JP4732131B2/ja
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  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2005321682A 2005-11-07 2005-11-07 同期回路システム Expired - Fee Related JP4732131B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005321682A JP4732131B2 (ja) 2005-11-07 2005-11-07 同期回路システム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005321682A JP4732131B2 (ja) 2005-11-07 2005-11-07 同期回路システム

Publications (3)

Publication Number Publication Date
JP2007129601A JP2007129601A (ja) 2007-05-24
JP2007129601A5 JP2007129601A5 (https=) 2008-12-18
JP4732131B2 true JP4732131B2 (ja) 2011-07-27

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ID=38151873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005321682A Expired - Fee Related JP4732131B2 (ja) 2005-11-07 2005-11-07 同期回路システム

Country Status (1)

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JP (1) JP4732131B2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8856578B2 (en) 2010-08-20 2014-10-07 Fujitsu Semiconductor Limited Integrated circuit device including skew adjustment circuit and skew adjustment method
US20160162214A1 (en) * 2014-12-08 2016-06-09 James A McCall Adjustable low swing memory interface

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3405778B2 (ja) * 1993-09-09 2003-05-12 セイレイ工業株式会社 コンバインの前処理装置
JPH0879048A (ja) * 1994-09-07 1996-03-22 Nec Eng Ltd 出力バッファ
JPH08186480A (ja) * 1994-12-28 1996-07-16 Nippon Seiki Co Ltd 半導体集積回路装置
JPH0993108A (ja) * 1995-09-28 1997-04-04 Toshiba Corp 入出力(i/o)バッファ回路
JP2000307395A (ja) * 1999-04-22 2000-11-02 Konica Corp 同期回路システム
JP2004334271A (ja) * 2003-04-30 2004-11-25 Fujitsu Ltd 半導体装置及びその設計方法

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Publication number Publication date
JP2007129601A (ja) 2007-05-24

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