JP4690326B2 - テンプレート層構成 - Google Patents

テンプレート層構成 Download PDF

Info

Publication number
JP4690326B2
JP4690326B2 JP2006528055A JP2006528055A JP4690326B2 JP 4690326 B2 JP4690326 B2 JP 4690326B2 JP 2006528055 A JP2006528055 A JP 2006528055A JP 2006528055 A JP2006528055 A JP 2006528055A JP 4690326 B2 JP4690326 B2 JP 4690326B2
Authority
JP
Japan
Prior art keywords
layer
silicon
germanium
wafer
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006528055A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007507109A (ja
JP2007507109A5 (enExample
Inventor
リウ，チュン−リ
サダカ，マリアム・ジー
バル，アレクサンダー・エル
ヌイェン，ビチ−イェン
シアン，ヴーン−ユー
トーマス，ショーン・ジー
ホワイト，テッド・アール
シー，キアンファ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Priority claimed from PCT/US2004/030088 external-priority patent/WO2005034191A2/en
Publication of JP2007507109A publication Critical patent/JP2007507109A/ja
Publication of JP2007507109A5 publication Critical patent/JP2007507109A5/ja
Application granted granted Critical
Publication of JP4690326B2 publication Critical patent/JP4690326B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2006528055A 2003-09-25 2004-09-14 テンプレート層構成 Expired - Fee Related JP4690326B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/670,928 2003-09-25
US10/670,928 US7029980B2 (en) 2003-09-25 2003-09-25 Method of manufacturing SOI template layer
US10/919,784 2004-08-17
US10/919,784 US7056778B2 (en) 2003-09-25 2004-08-17 Semiconductor layer formation
PCT/US2004/030088 WO2005034191A2 (en) 2003-09-25 2004-09-14 Template layer formation

Publications (3)

Publication Number Publication Date
JP2007507109A JP2007507109A (ja) 2007-03-22
JP2007507109A5 JP2007507109A5 (enExample) 2007-11-08
JP4690326B2 true JP4690326B2 (ja) 2011-06-01

Family

ID=34376030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006528055A Expired - Fee Related JP4690326B2 (ja) 2003-09-25 2004-09-14 テンプレート層構成

Country Status (4)

Country Link
US (3) US7029980B2 (enExample)
JP (1) JP4690326B2 (enExample)
CN (1) CN1926660B (enExample)
TW (1) TWI387848B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899272B2 (en) 2015-09-24 2018-02-20 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices including complementary metal oxide semiconductor transistors

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
US7598513B2 (en) * 2003-06-13 2009-10-06 Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University, A Corporate Body Organized Under Arizona Law SixSnyGe1-x-y and related alloy heterostructures based on Si, Ge and Sn
US7078300B2 (en) * 2003-09-27 2006-07-18 International Business Machines Corporation Thin germanium oxynitride gate dielectric for germanium-based devices
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7217949B2 (en) * 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
JP4958797B2 (ja) * 2005-02-24 2012-06-20 ソイテック ＳｉＧｅ層の表面領域を酸化させる方法、ＳＧＯＩ構造体内の少なくとも１つの接合境界面を安定化させる方法、及びＳｉＧｅ層を半導体材料製の基板層と接合する方法
US20060228492A1 (en) * 2005-04-07 2006-10-12 Sumco Corporation Method for manufacturing SIMOX wafer
FR2891281B1 (fr) * 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
WO2007053381A1 (en) * 2005-10-31 2007-05-10 Advanced Micro Devices, Inc. Technique for strain engineering in si-based transistors by using embedded semiconductor layers including atoms with high covalent radius
DE102005051994B4 (de) * 2005-10-31 2011-12-01 Globalfoundries Inc. Verformungsverfahrenstechnik in Transistoren auf Siliziumbasis unter Anwendung eingebetteter Halbleiterschichten mit Atomen mit einem großen kovalenten Radius
US7265004B2 (en) * 2005-11-14 2007-09-04 Freescale Semiconductor, Inc. Electronic devices including a semiconductor layer and a process for forming the same
FR2898215B1 (fr) * 2006-03-01 2008-05-16 Commissariat Energie Atomique Procede de fabrication d'un substrat par condensation germanium
FR2899017A1 (fr) * 2006-03-21 2007-09-28 St Microelectronics Sa Procede de realisation d'un transistor a canal comprenant du germanium
US7882382B2 (en) * 2006-06-14 2011-02-01 International Business Machines Corporation System and method for performing computer system maintenance and service
US7629220B2 (en) 2006-06-30 2009-12-08 Freescale Semiconductor, Inc. Method for forming a semiconductor device and structure thereof
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
US7560354B2 (en) * 2007-08-08 2009-07-14 Freescale Semiconductor, Inc. Process of forming an electronic device including a doped semiconductor layer
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
US20090191468A1 (en) * 2008-01-29 2009-07-30 International Business Machines Corporation Contact Level Mask Layouts By Introducing Anisotropic Sub-Resolution Assist Features
US20090250760A1 (en) * 2008-04-02 2009-10-08 International Business Machines Corporation Methods of forming high-k/metal gates for nfets and pfets
US20090289280A1 (en) * 2008-05-22 2009-11-26 Da Zhang Method for Making Transistors and the Device Thereof
US8003454B2 (en) * 2008-05-22 2011-08-23 Freescale Semiconductor, Inc. CMOS process with optimized PMOS and NMOS transistor devices
US7975246B2 (en) * 2008-08-14 2011-07-05 International Business Machines Corporation MEEF reduction by elongation of square shapes
US8440547B2 (en) 2009-02-09 2013-05-14 International Business Machines Corporation Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
FR2947098A1 (fr) * 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US8623728B2 (en) 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8647439B2 (en) 2012-04-26 2014-02-11 Applied Materials, Inc. Method of epitaxial germanium tin alloy surface preparation
US9231063B2 (en) 2014-02-24 2016-01-05 International Business Machines Corporation Boron rich nitride cap for total ionizing dose mitigation in SOI devices
TWI531071B (zh) * 2014-07-08 2016-04-21 Univ Nat Central Fabrication method of gold - oxygen half - gate stacking structure
US9305781B1 (en) 2015-04-30 2016-04-05 International Business Machines Corporation Structure and method to form localized strain relaxed SiGe buffer layer
US10541172B2 (en) 2016-08-24 2020-01-21 International Business Machines Corporation Semiconductor device with reduced contact resistance
US9799618B1 (en) 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
US10930793B2 (en) * 2017-04-21 2021-02-23 International Business Machines Corporation Bottom channel isolation in nanosheet transistors

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002094076A (ja) * 2000-06-12 2002-03-29 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ及び半導体装置
JP2003023160A (ja) * 2001-07-06 2003-01-24 Toshiba Corp 電界効果トランジスタの製造方法、電界効果トランジスタ及び集積回路素子
JP2004363199A (ja) * 2003-06-02 2004-12-24 Sumitomo Mitsubishi Silicon Corp 半導体基板の製造方法

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3912559A (en) * 1971-11-25 1975-10-14 Suwa Seikosha Kk Complementary MIS-type semiconductor devices and methods for manufacturing same
US4851257A (en) * 1987-03-13 1989-07-25 Harris Corporation Process for the fabrication of a vertical contact
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5534713A (en) 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
DE59707274D1 (de) 1996-09-27 2002-06-20 Infineon Technologies Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US5906951A (en) 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5943565A (en) 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US5846857A (en) 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US6124627A (en) 1998-12-03 2000-09-26 Texas Instruments Incorporated Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region
US6259138B1 (en) 1998-12-18 2001-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having multilayered gate electrode and impurity regions overlapping therewith
JP3884203B2 (ja) 1998-12-24 2007-02-21 株式会社東芝 半導体装置の製造方法
US6369438B1 (en) 1998-12-24 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2001036054A (ja) 1999-07-19 2001-02-09 Mitsubishi Electric Corp Ｓｏｉ基板の製造方法
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
KR100392166B1 (ko) 2000-03-17 2003-07-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법 및 반도체 장치
US6524935B1 (en) 2000-09-29 2003-02-25 International Business Machines Corporation Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique
US6890835B1 (en) 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
KR100720095B1 (ko) * 2000-11-07 2007-05-18 삼성전자주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
US7312485B2 (en) 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US20020168802A1 (en) * 2001-05-14 2002-11-14 Hsu Sheng Teng SiGe/SOI CMOS and method of making the same
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
JP2003031495A (ja) 2001-07-12 2003-01-31 Hitachi Ltd 半導体装置用基板の製造方法および半導体装置の製造方法
US6475870B1 (en) 2001-07-23 2002-11-05 Taiwan Semiconductor Manufacturing Company P-type LDMOS device with buried layer to solve punch-through problems and process for its manufacture
EP1428262A2 (en) 2001-09-21 2004-06-16 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6515335B1 (en) 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US6562703B1 (en) 2002-03-13 2003-05-13 Sharp Laboratories Of America, Inc. Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content
US6743651B2 (en) 2002-04-23 2004-06-01 International Business Machines Corporation Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen
US6638802B1 (en) 2002-06-20 2003-10-28 Intel Corporation Forming strained source drain junction field effect transistors
JP3873012B2 (ja) * 2002-07-29 2007-01-24 株式会社東芝 半導体装置の製造方法
US6955952B2 (en) 2003-03-07 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
US7026249B2 (en) 2003-05-30 2006-04-11 International Business Machines Corporation SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth
US7049660B2 (en) 2003-05-30 2006-05-23 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature
KR20060056331A (ko) * 2003-07-23 2006-05-24 에이에스엠 아메리카, 인코포레이티드 절연체-상-실리콘 구조 및 벌크 기판 상의 ＳｉＧｅ 증착

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002094076A (ja) * 2000-06-12 2002-03-29 Semiconductor Energy Lab Co Ltd 薄膜トランジスタ及び半導体装置
JP2003023160A (ja) * 2001-07-06 2003-01-24 Toshiba Corp 電界効果トランジスタの製造方法、電界効果トランジスタ及び集積回路素子
JP2004363199A (ja) * 2003-06-02 2004-12-24 Sumitomo Mitsubishi Silicon Corp 半導体基板の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899272B2 (en) 2015-09-24 2018-02-20 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices including complementary metal oxide semiconductor transistors

Also Published As

Publication number Publication date
JP2007507109A (ja) 2007-03-22
CN1926660B (zh) 2011-06-22
US20050070056A1 (en) 2005-03-31
US20050070053A1 (en) 2005-03-31
CN1926660A (zh) 2007-03-07
US20050070057A1 (en) 2005-03-31
US7029980B2 (en) 2006-04-18
TW200513791A (en) 2005-04-16
TWI387848B (zh) 2013-03-01
US7056778B2 (en) 2006-06-06
US7208357B2 (en) 2007-04-24

Similar Documents

Publication Publication Date Title
JP4690326B2 (ja) テンプレート層構成
JP6248212B2 (ja) Оｎｏスタックの形成方法
KR101295503B1 (ko) 금속 소스/드레인에 의해 형성된 단축 변형을 갖는 양자 우물 ｍｏｓｆｅｔ 채널 및 등각 재성장 소스/드레인
US6740913B2 (en) MOS transistor using mechanical stress to control short channel effects
US6228694B1 (en) Method of increasing the mobility of MOS transistors by use of localized stress regions
KR101811796B1 (ko) 급경사 접합 프로파일을 갖는 소스/드레인 영역들을 구비하는 반도체 소자 및 그 제조방법
KR101180978B1 (ko) 구동 전류 감손 없이 임계 안정성이 증가된 트랜지스터 디바이스
JP2008511173A (ja) 移動度を半導体素子において増加させる方法及び装置
JP2008283182A (ja) Ｐｍｏｓトランジスタ製造方法及びｃｍｏｓトランジスタ製造方法
CN101276758A (zh) 制作半导体晶体管元件的方法
KR101339998B1 (ko) 반도체 소자 및 그 제조 방법
JP2008177319A (ja) 半導体装置の製造方法および半導体装置
KR100630767B1 (ko) 에피택셜 영역을 구비하는 모스 트랜지스터의 제조방법
US6150221A (en) Semiconductor device and method for manufacturing same
JPH10256539A (ja) 半導体装置及びその製造方法
JPH11103050A (ja) 半導体装置及びその製造方法
JP2006253318A (ja) ｐチャネルＭＯＳトランジスタおよびその製造方法
US7691714B2 (en) Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
JP4031408B2 (ja) Ｍｏｓトランジスタの製造方法
JP5034332B2 (ja) 半導体装置の製造方法
KR101132603B1 (ko) 템플릿 층 형성
JP3354535B2 (ja) 半導体装置の製造方法
JP2016004952A (ja) 半導体装置の製造方法
JP2001250945A (ja) 半導体装置及びその製造方法
JP3031723B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070913

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070913

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100715

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100720

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20101019

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20101026

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101122

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110119

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110217

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140225

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees