JP4668782B2 - 実装基板の製造方法 - Google Patents

実装基板の製造方法 Download PDF

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Publication number
JP4668782B2
JP4668782B2 JP2005363411A JP2005363411A JP4668782B2 JP 4668782 B2 JP4668782 B2 JP 4668782B2 JP 2005363411 A JP2005363411 A JP 2005363411A JP 2005363411 A JP2005363411 A JP 2005363411A JP 4668782 B2 JP4668782 B2 JP 4668782B2
Authority
JP
Japan
Prior art keywords
layer
mounting
wiring
support substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005363411A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007165776A5 (enExample
JP2007165776A (ja
Inventor
功一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2005363411A priority Critical patent/JP4668782B2/ja
Priority to US11/610,244 priority patent/US7410837B2/en
Priority to TW095147046A priority patent/TW200730065A/zh
Publication of JP2007165776A publication Critical patent/JP2007165776A/ja
Publication of JP2007165776A5 publication Critical patent/JP2007165776A5/ja
Application granted granted Critical
Publication of JP4668782B2 publication Critical patent/JP4668782B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0156—Temporary polymeric carrier or foil, e.g. for processing or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1581—Treating the backside of the PCB, e.g. for heating during soldering or providing a liquid coating on the backside
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2005363411A 2005-12-16 2005-12-16 実装基板の製造方法 Expired - Fee Related JP4668782B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005363411A JP4668782B2 (ja) 2005-12-16 2005-12-16 実装基板の製造方法
US11/610,244 US7410837B2 (en) 2005-12-16 2006-12-13 Method of manufacturing mounting substrate
TW095147046A TW200730065A (en) 2005-12-16 2006-12-15 Method of manufacturing mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005363411A JP4668782B2 (ja) 2005-12-16 2005-12-16 実装基板の製造方法

Publications (3)

Publication Number Publication Date
JP2007165776A JP2007165776A (ja) 2007-06-28
JP2007165776A5 JP2007165776A5 (enExample) 2008-11-13
JP4668782B2 true JP4668782B2 (ja) 2011-04-13

Family

ID=38174163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005363411A Expired - Fee Related JP4668782B2 (ja) 2005-12-16 2005-12-16 実装基板の製造方法

Country Status (3)

Country Link
US (1) US7410837B2 (enExample)
JP (1) JP4668782B2 (enExample)
TW (1) TW200730065A (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201325338A (zh) * 2011-12-14 2013-06-16 Wistron Corp 避免金手指結構沾錫之電路板
US8889484B2 (en) * 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
US9642261B2 (en) * 2014-01-24 2017-05-02 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Composite electronic structure with partially exposed and protruding copper termination posts
US9508703B2 (en) * 2014-04-30 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked dies with wire bonds and method
KR102192569B1 (ko) * 2015-11-06 2020-12-17 삼성전자주식회사 전자 부품 패키지 및 그 제조방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11112152A (ja) 1997-10-03 1999-04-23 Matsushita Electric Ind Co Ltd フリップチップ実装の多層プリント基板
JP2001119131A (ja) * 1999-10-20 2001-04-27 Matsushita Electric Ind Co Ltd 電子部品実装体とそれを用いた電子機器と電子部品実装体の製造方法
JP2002261440A (ja) * 2001-03-01 2002-09-13 Sony Chem Corp フレキシブル配線基板の製造方法及びフレキシブル配線基板
US7474538B2 (en) * 2002-05-27 2009-01-06 Nec Corporation Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package
JP4043872B2 (ja) * 2002-07-11 2008-02-06 大日本印刷株式会社 多層配線基板の製造方法および樹脂封止型半導体装置の製造方法
JP4137659B2 (ja) * 2003-02-13 2008-08-20 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4483247B2 (ja) * 2003-09-22 2010-06-16 凸版印刷株式会社 多層フレキシブル配線基板の製造方法及び多層フレキシブル配線基板
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP2005315775A (ja) * 2004-04-30 2005-11-10 Fujitsu Autom Ltd 片面移動式プローブを用いた４端子検査方法及び４端子検査用治具
JP4108643B2 (ja) * 2004-05-12 2008-06-25 日本電気株式会社 配線基板及びそれを用いた半導体パッケージ

Also Published As

Publication number Publication date
TW200730065A (en) 2007-08-01
US7410837B2 (en) 2008-08-12
JP2007165776A (ja) 2007-06-28
US20070141758A1 (en) 2007-06-21

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