JP4632122B2 - モジュール - Google Patents
モジュール Download PDFInfo
- Publication number
- JP4632122B2 JP4632122B2 JP2004365004A JP2004365004A JP4632122B2 JP 4632122 B2 JP4632122 B2 JP 4632122B2 JP 2004365004 A JP2004365004 A JP 2004365004A JP 2004365004 A JP2004365004 A JP 2004365004A JP 4632122 B2 JP4632122 B2 JP 4632122B2
- Authority
- JP
- Japan
- Prior art keywords
- module
- reference voltage
- power supply
- semiconductor device
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
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- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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Description
図1〜図11を用いて、実施の形態1におけるメモリモジュールの一例を説明する。なお、図6〜図11は、本発明の特徴を分かり易くするために、本発明の比較対象となる従来技術を説明するための図である。
図12を用いて、実施の形態2におけるメモリモジュールの一例を説明する。
図13を用いて、実施の形態3におけるメモリモジュールの一例を説明する。
図14を用いて、実施の形態4におけるメモリモジュールの一例を説明する。
実施の形態1から実施の形態4までは、マザーボードからVref電圧を供給する方式における低ノイズ配線方式であった。実施の形態5から8は、モジュール内部でVrefを生成するときの配線方式を実現する。基本的には、実施の形態1から4の考えを内部生成用に置き換えたものである。ここで、Vref内部生成とは、Vrefは通常メモリの電源電圧Vddの1/2の電圧値を持つため、モジュール内のVddとVssをテブナン終端することで生成することである。ここで、テブナン終端は、同じ抵抗値を持つ2つの抵抗でVref配線(プレーン)をVddとVssにそれぞれ繋ぐことである。
図16を用いて、実施の形態6におけるメモリモジュールの一例を説明する。
図17を用いて、実施の形態7におけるメモリモジュールの一例を説明する。
図18を用いて、実施の形態8におけるメモリモジュールの一例を説明する。
実施の形態9から実施の形態14までは、実施の形態1から実施の形態8までの配線方式をレジスタやバッファを有するモジュールに適用した場合である。ここで、レジスタやバッファは高速化するメモリの動作を安定させるために、マザーボードからモジュールに転送されたアドレス、クロックや、データ信号等を溜め込み、モジュール内で分配するためのチップである。
図20を用いて、実施の形態10におけるメモリモジュールの一例を説明する。
図21を用いて、実施の形態11におけるメモリモジュールの一例を説明する。
図22を用いて、実施の形態12におけるメモリモジュールの一例を説明する。
図23を用いて、実施の形態13におけるメモリモジュールの一例を説明する。
実施の形態14から実施の形態21は、Viaで上下間の電気的な接続を行っている3次元実装タイプのモジュールにおける本発明の実施の形態である。
図25を用いて、実施の形態15におけるメモリモジュールの一例を説明する。
図26を用いて、実施の形態16におけるメモリモジュールの一例を説明する。
図27を用いて、実施の形態17におけるメモリモジュールの一例を説明する。
図28を用いて、実施の形態18におけるメモリモジュールの一例を説明する。
図29を用いて、実施の形態19におけるメモリモジュールの一例を説明する。
図30を用いて、実施の形態20におけるメモリモジュールの一例を説明する。
図31を用いて、実施の形態21におけるメモリモジュールの一例を説明する。
実施の形態22から実施の形態23は、マルチチップモジュールの場合の実施の形態である。
図33を用いて、実施の形態23におけるメモリモジュールの一例を説明する。
Claims (21)
- 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記参照電圧は、前記システム基板から前記参照電圧電源面に供給されている、
ことを特徴とするモジュール。 - 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記参照電圧は、前記システム基板から前記参照電圧電源面に供給されており、
前記モジュール基板上で隣接して実装されている半導体装置の個別の参照電圧電源面が、チップ抵抗あるいはチップインダクタンスあるいは長い信号線で接続されている、
ことを特徴とするモジュール。 - 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記参照電圧は、前記システム基板から前記参照電圧電源面に供給されており、
前記モジュール基板上には前記半導体装置が個別に有する第1の参照電圧電源面の他に第2の参照電圧電源面があり、
前記第2の参照電圧電源面にはデカップリングコンデンサが実装され、
前記第2の参照電圧電源面と前記半導体装置が個別に有する第1の参照電圧電源面との間を個々に配線で接続している、
ことを特徴とするモジュール。 - 請求項3記載のモジュールにおいて、
前記配線が前記第2の参照電圧電源面から前記第1の参照電圧電源面に接続する途中にチップ抵抗あるいはチップインダクタンスを有することを特徴とするモジュール。 - 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記参照電圧は、前記システム基板から前記参照電圧電源面に供給されており、
前記モジュール基板上で隣接して実装されている半導体装置の個別の参照電圧電源面及び前記半導体装置の参照電圧入力部が配線で従属接続されており、
前記配線には隣接する前記半導体装置間にチップ抵抗あるいはチップインダクタンスを有する、
ことを特徴とするモジュール。 - 請求項2〜5のいずれか1項記載のモジュールにおいて、
前記モジュール基板において参照電圧を複数の半導体装置に配線するための配線経路に実装されているチップ抵抗の値Rが、
配線経路のインダクタンスLと前記半導体装置の近傍に実装されているデカップリングコンデンサの容量Cdecとの関係で、
を満たすことを特徴とするモジュール。 - 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記モジュール基板は前記システム基板から参照電圧を供給されており、
前記モジュール基板の前記システム基板からの参照電圧入力部と前記モジュール基板に実装されている1つ目の前記半導体装置との間に、低域通過フィルタまたはチップ抵抗またはチップインダクタンスを有する、
ことを特徴とするモジュール。 - 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記モジュール基板上にある参照電圧電源面の一つが前記モジュール基板の電源面とグランド面との間に同じ値の抵抗を有し、
電源電圧の半分の電圧値を参照電圧として内部生成する、
ことを特徴とするモジュール。 - 請求項1〜8のいずれか1項記載のモジュールにおいて、
前記モジュール基板には前記半導体装置の高速動作を補助するためのレジスタまたはバッファが実装されており、
前記レジスタまたは前記バッファの近傍に参照電圧電源面を配置しない、
ことを特徴とするモジュール。 - 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記参照電圧は、前記システム基板から前記参照電圧電源面に供給されており、
前記モジュール基板と前記システム基板との間を電気的に接続するためのインターポーザ基板を有し、
前記半導体装置を封止したサブ基板が複数有り、
前記サブ基板は前記インターポーザ基板を最下層として積層方向に実装され、
前記サブ基板間はViaで電気的に接続されている、
ことを特徴とするモジュール。 - 請求項10記載のモジュールにおいて、
前記インターポーザ基板と複数の前記サブ基板との間の参照電圧配線は一つのViaで接続されており、
前記サブ基板の参照電圧配線は前記サブ基板上で配線の配線経路が長くなるように配置され、
前記配線は隣接するサブ基板で配線経路が長くなるように配置され、
前記配線にはデカップリングコンデンサが実装され、
前記サブ基板の内層には参照電圧電源面を有する、
ことを特徴とするモジュール。 - 請求項11記載のモジュールにおいて、
前記サブ基板の参照電圧配線の配線経路にチップ抵抗あるいはチップインダクタンスを有することを特徴とするモジュール。 - 請求項10記載のモジュールにおいて、
前記インターポーザ基板と複数の前記サブ基板との間の参照電圧配線はサブ基板毎に個別のViaで接続されていることを特徴とするモジュール。 - 請求項13記載のモジュールにおいて、
前記サブ基板の参照電圧配線の配線経路にチップ抵抗あるいはチップインダクタンスを有することを特徴とするモジュール。 - 請求項12または14記載のモジュールにおいて、
前記モジュール基板において参照電圧を複数の半導体装置に配線するための配線経路に実装されているチップ抵抗の値Rが、
各サブ基板とインターポーザ基板の配線経路のインダクタンスLと前記半導体装置の近傍に実装されているデカップリングコンデンサの容量Cdecとの関係で、
を満たすことを特徴とするモジュール。 - 請求項10〜15のいずれか1項記載のモジュールにおいて、
前記モジュール基板の参照電圧経路において前記インターポーザ基板における参照電圧入力部と前記サブ基板に接続するためのViaとの間に、低域通過フィルタまたはチップ抵抗またはチップインダクタンスを有する、
ことを特徴とするモジュール。 - 参照電圧を用いる半導体装置と、前記半導体装置を複数実装するモジュール基板とからなるモジュールであって、
前記モジュール基板はシステム基板に実装され、
前記モジュール基板に実装された複数の前記半導体装置の参照電圧入力部にはデカップリングコンデンサ及びVss層と平行平板を構成する参照電圧電源面が接続され、
前記デカップリングコンデンサと前記参照電圧電源面を前記半導体装置毎に個別にそれぞれ前記半導体装置の近傍に有しており、
前記モジュール基板と前記システム基板との間を電気的に接続するためのインターポーザ基板を有し、
前記半導体装置を封止したサブ基板が複数有り、
前記サブ基板は前記インターポーザ基板を最下層として積層方向に実装され、
前記サブ基板間はViaで電気的に接続されており、
前記インターポーザ基板上にある参照電圧経路が前記インターポーザ基板の電源面とグランド面との間に同じ値の抵抗を有し、
電源電圧の半分の電圧値を参照電圧として内部生成する、
ことを特徴とするモジュール。 - 請求項1記載のモジュールにおいて、
前記モジュール基板と前記システム基板との間を電気的に接続するためのインターポーザ基板を有し、
前記半導体装置を封止したサブ基板が複数有り、
前記サブ基板は前記インターポーザ基板を最下層として積層方向に実装され、
前記サブ基板間はワイヤで電気的に接続されている、
ことを特徴とするモジュール。 - 請求項18記載のモジュールにおいて、
前記インターポーザ基板と複数の前記サブ基板との間の参照電圧配線にはチップ抵抗が実装されていることを特徴とするモジュール。 - 請求項18記載のモジュールにおいて、
前記インターポーザ基板と複数の前記サブ基板との間の参照電圧配線はサブ基板毎に個別のワイヤを有し、
各ワイヤと前記インターポーザ基板の間にはチップ抵抗が実装されている、
ことを特徴とするモジュール。 - 請求項19または20記載のモジュールにおいて、
前記モジュール基板において参照電圧を複数の半導体装置に配線するための配線経路に実装されているチップ抵抗の値Rが、
各サブ基板とインターポーザ基板の配線経路のインダクタンスLと前記半導体装置の近傍に実装されているデカップリングコンデンサの容量Cdecとの関係で、
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US7447038B2 (en) | 2008-11-04 |
US20060133055A1 (en) | 2006-06-22 |
JP2006173409A (ja) | 2006-06-29 |
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