JP4621613B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4621613B2 JP4621613B2 JP2006064430A JP2006064430A JP4621613B2 JP 4621613 B2 JP4621613 B2 JP 4621613B2 JP 2006064430 A JP2006064430 A JP 2006064430A JP 2006064430 A JP2006064430 A JP 2006064430A JP 4621613 B2 JP4621613 B2 JP 4621613B2
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Description
前記ゲート絶縁膜、第1のゲート電極膜、およびストッパー膜を貫通して前記半導体基板に達するように素子分離溝を形成する工程、
前記ストッパー膜上に、シリコン含有化合物を溶剤に溶解してなる塗布液を供給する工程、
前記半導体基板を回転させて、前記シリコン含有化合物を含む塗布膜を形成する工程、
前記半導体基板の裏面に、少なくとも一部がα−ピネンであるリンス液を供給してバックリンスを施し、裏面を洗浄する工程、
前記バックリンス後の前記半導体基板を乾燥して前記リンス液を除去する工程、
前記半導体基板を熱処理して前記塗布膜から前記溶剤を除去し、前記シリコン含有化合物を含む絶縁膜を得る工程、
前記シリコン化合物を含む絶縁膜を酸化処理して、二酸化シリコン膜に変化させる工程、
前記ストッパー膜上の前記二酸化シリコン膜を除去して前記素子分離溝内に前記二酸化シリコン膜を残置し、素子分離絶縁膜を形成する工程、
前記ストッパー膜を除去して、前記第1のゲート電極膜の表面を露出する工程、
前記素子分離絶縁膜の上部を除去して、前記第1のゲート電極膜の側面の上部を露出する工程、
前記側面の上部が露出した第1のゲート電極膜および前記上部が除去された素子分離絶縁膜の上に、電極間絶縁膜を形成する工程、および
前記電極間絶縁膜の上に第2のゲート電極膜を形成する工程を具備することを特徴とする。
図1乃至図8を参照して、塗布工程のフローを説明する。
上記一般式(1)中、R1、R2およびR3は、同一でも異なっていてもよく、それぞれ水素原子または置換基である。置換基としては、例えば、アルキル基やアルコキシ基、アルケニル基、水酸基、アミノ基などが挙げられる。
まず、いくつかの化合物の溶液をリンス液として用いて、シリコン含有化合物を含む塗布膜に対する特性を調べた。シリコン含有化合物としては、AZエレクトロニックマテリアルズ社製のペルヒドロポリシラザン(PHPS)を準備した。これを、溶剤としてのジ−n−ブチルエーテルに溶解して塗布液を調製した。
次に、コーターの材質との相性について調べた。薬液チューブや廃液タンクなど薬品と接触する部分は、ほとんどがフッ素系樹脂製または金属製である。このため、上述したいずれの化合物を使用しても問題は生じない。しかしながら、コーターカップのみはポリプロピレン(PP)製である。物質によっては、このPPを膨潤させコーターカップの変形を招くおそれがある。そこで、コーターカップの断片を用いて浸漬試験を行なって、PP耐性を調べた。
EBRとバックリンスに2種類のリンス液(ナフタレン系溶剤、α−ピネン)を組み合わせたときのスループット性および経済性を調べた。スループット性は、EBRとバックリンス後の乾燥とに必要な時間を見積もることによって評価できる。
本実施形態においては、純度97%以上のα−d−ピネンをリンス液として用いて、PHPSを含む塗布絶縁膜を形成した。塗布液としては、前述の予備実験1と同様のPHPSをジ−n−ブチルエーテルに溶解して得られた溶液を用いる。
次に、図4に示すようにウェハ7を1200rpmで回転させつつ、1ml/sの流量で2秒間塗布液をウェハ7上に吐出する。さらに、100rpmで短時間回転させて、図5に示すようにウェハ7の全面に塗布膜8を形成する。塗布液の吐出量は1.5mlである。所望の膜厚で塗布膜8が得られるように、任意の回転数で13秒間、ウェハ7を回転させる。塗布膜8は、溶剤を蒸発させながら乾燥し、最後に一定の膜厚に落ち着く。そのため、ある程度の回転時間が必要とされ、膜厚はこの回転数を変えることによって調節することができる。300mmウェハの場合、回転数は500〜4000rpmの間である。
以下、STI(Shallow Trench Isolation)埋め込み方法の実施形態を説明する。まず図9乃至図12を参照して、CMOS構造のメモリセルを製造する手順を説明する。
図13乃至図17を参照して、NAND構造のメモリセルを製造する手順を説明する。
図18乃至図22を参照して、ポリシラザン(PSZ)を使用してPMD(Pre−Metal Dielectric)を形成する手順を説明する。
図23乃至図25を参照して、ポリシラザン(PSZ)を使用してIMD(Inter−Metal Dielectric)を形成する手順を説明する。
3b…バックサイドリンスノズル; 4…ソルベントバス; 5…薬液ノズル
6…ダミーディスペンスポート; 7…半導体ウェハ; 8…塗布膜; 9…リンス液
S…塗布液; 10…シリコン基板; 11…SiO2膜
12…CMPストッパー膜; 13…STI溝
15…ペルヒドロポリシラザン(PHPS)膜; 16…SiO2膜
18…ゲート絶縁膜; 19…第1のゲート(浮遊ゲート)電極膜
20…電極間絶縁膜; 21…第2のゲート(制御ゲート)電極膜
24…シリコン基板; 25a,25b…不純物領域; 26…ゲート電極
27…層間絶縁膜; 28…ポリシラザン(PSZ)膜; 29…SiN膜
30…コンタクトホール; 31…配線; 32…層間絶縁膜; 34…シリコン基板
35…メタル配線; 36…SiN膜; 37…PSZ膜; 38…コンタクトホール
39…メタル配線; 40…SiO2膜; 41…SiO2膜。
Claims (5)
- 半導体基板上に、ゲート絶縁膜、第1のゲート電極膜、およびストッパー膜を順次形成する工程、
前記ゲート絶縁膜、第1のゲート電極膜、およびストッパー膜を貫通して前記半導体基板に達するように素子分離溝を形成する工程、
前記ストッパー膜上に、シリコン含有化合物を溶剤に溶解してなる塗布液を供給する工程、
前記半導体基板を回転させて、前記シリコン含有化合物を含む塗布膜を形成する工程、
前記半導体基板の裏面に、少なくとも一部がα−ピネンであるリンス液を供給してバックリンスを施し、裏面を洗浄する工程、
前記バックリンス後の前記半導体基板を乾燥して前記リンス液を除去する工程、
前記半導体基板を熱処理して前記塗布膜から前記溶剤を除去し、前記シリコン含有化合物を含む絶縁膜を得る工程、
前記シリコン化合物を含む絶縁膜を酸化処理して、二酸化シリコン膜に変化させる工程、
前記ストッパー膜上の前記二酸化シリコン膜を除去して前記素子分離溝内に前記二酸化シリコン膜を残置し、素子分離絶縁膜を形成する工程、
前記ストッパー膜を除去して、前記第1のゲート電極膜の表面を露出する工程、
前記素子分離絶縁膜の上部を除去して、前記第1のゲート電極膜の側面の上部を露出する工程、
前記側面の上部が露出した第1のゲート電極膜および前記上部が除去された素子分離絶縁膜の上に、電極間絶縁膜を形成する工程、および
前記電極間絶縁膜の上に第2のゲート電極膜を形成する工程
を具備することを特徴とする半導体装置の製造方法。 - 前記塗布膜が形成された前記半導体基板のエッジ部分に、少なくとも一部がα−ピネンであるリンス液を供給して、エッジカットを行なう工程をさらに具備することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記シリコン化合物を含む絶縁膜の前記酸化処理は、230℃以上900℃以下の温度で行なわれることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記ストッパー膜上の前記二酸化シリコン膜を除去することは、CMPにより行なわれることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。
- 前記第1のゲート電極膜は、多結晶シリコン膜、WSi,およびCoSiからなる群から選択される材料を用いて形成されることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
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