JP4599121B2 - 電気中継板 - Google Patents
電気中継板 Download PDFInfo
- Publication number
- JP4599121B2 JP4599121B2 JP2004260871A JP2004260871A JP4599121B2 JP 4599121 B2 JP4599121 B2 JP 4599121B2 JP 2004260871 A JP2004260871 A JP 2004260871A JP 2004260871 A JP2004260871 A JP 2004260871A JP 4599121 B2 JP4599121 B2 JP 4599121B2
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- JP
- Japan
- Prior art keywords
- ceramic substrate
- relay plate
- electrical relay
- interposer
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
セラミック基板と、
前記セラミック基板の上面と下面とを貫通する貫通孔と、
前記上面に取り付けられる第1電子部品と前記下面に取り付けられる第2電子部品とを電気的に接続するように前記貫通孔の内壁に形成された管状導体ビアと、
前記管状導体ビアの管内に低弾性率材料を充填してなる応力緩和部と、
を備えたものである。
Claims (8)
- セラミック基板と、
前記セラミック基板の上面と下面とを貫通する貫通孔と、
前記上面に取り付けられる第1電子部品と前記下面に取り付けられる第2電子部品とを電気的に接続するように前記貫通孔の内壁に形成された管状導体ビアと、
前記管状導体ビアの管内に低弾性率材料を充填してなる応力緩和部と、
を備え、
前記応力緩和部は30℃におけるヤング率が10MPa〜1GPaの低弾性率材料からなる電気中継板。 - 前記貫通孔はクビレを持つ形状に形成されている、請求項1に記載の電気中継板。
- 前記貫通孔の直径Dに対する前記管状導体ビアの厚さtの比t/Dは1/40≦t/D≦1/3を満たす、請求項1又は2に記載の電気中継板。
- 前記貫通孔の直径Dは50μm≦D≦200μmを満たす、請求項1〜3のいずれかに記載の電気中継板。
- 前記セラミック基板の厚みTcに対する前記応力緩和部の直径dの比d/Tcは1/10≦d/Tc≦1を満たす、請求項1〜4のいずれかに記載の電気中継板。
- −55℃×30分のあと125℃×30分を1サイクルとするヒートサイクル試験を1000サイクル繰り返したあとにクラックが未発生である、請求項1〜5のいずれかに記載の電気中継板。
- 前記第1電子部品及び前記第2電子部品を鉛フリーはんだを介してリフローにより接続したときにクラックが未発生である、請求項1〜6のいずれかに記載の電気中継板。
- 前記第1電子部品は半導体素子であり、前記第2電子部品はプリント配線板である、請求項1〜7のいずれかに記載の電気中継板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004260871A JP4599121B2 (ja) | 2004-09-08 | 2004-09-08 | 電気中継板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004260871A JP4599121B2 (ja) | 2004-09-08 | 2004-09-08 | 電気中継板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006080199A JP2006080199A (ja) | 2006-03-23 |
JP4599121B2 true JP4599121B2 (ja) | 2010-12-15 |
Family
ID=36159424
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004260871A Active JP4599121B2 (ja) | 2004-09-08 | 2004-09-08 | 電気中継板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4599121B2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
KR100872130B1 (ko) * | 2007-07-05 | 2008-12-08 | 삼성전기주식회사 | 관통전극 형성방법 및 인쇄회로기판 제조방법 |
JP5019995B2 (ja) * | 2007-08-27 | 2012-09-05 | 京セラ株式会社 | 配線基板、実装基板および実装構造体、並びに配線基板の製造方法 |
JP2009074823A (ja) * | 2007-09-19 | 2009-04-09 | Ngk Spark Plug Co Ltd | 電子部品検査装置用配線基板およびその製造方法 |
JP5108433B2 (ja) * | 2007-09-25 | 2012-12-26 | 日本特殊陶業株式会社 | 電子部品検査装置用配線基板 |
WO2010027075A1 (ja) * | 2008-09-05 | 2010-03-11 | 日本発條株式会社 | 配線基板およびプローブカード |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62243394A (ja) * | 1986-04-15 | 1987-10-23 | キヤノン株式会社 | プリント配線板の製造方法 |
JPH1197843A (ja) * | 1997-09-16 | 1999-04-09 | Kyocera Corp | 多層配線基板 |
JP2000174052A (ja) * | 1998-09-30 | 2000-06-23 | Ibiden Co Ltd | 半導体チップ及び半導体チップの製造方法 |
JP2000200848A (ja) * | 1999-01-06 | 2000-07-18 | Shinko Electric Ind Co Ltd | 電子部品実装用回路基板及び半導体装置 |
JP2001168224A (ja) * | 1999-12-08 | 2001-06-22 | Sony Corp | 半導体装置、電子回路装置および製造方法 |
JP2001210953A (ja) * | 2000-01-27 | 2001-08-03 | Ngk Spark Plug Co Ltd | 配線基板及び配線基板の製造方法 |
JP2004047667A (ja) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | 多層配線基板およびその製造方法 |
-
2004
- 2004-09-08 JP JP2004260871A patent/JP4599121B2/ja active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62243394A (ja) * | 1986-04-15 | 1987-10-23 | キヤノン株式会社 | プリント配線板の製造方法 |
JPH1197843A (ja) * | 1997-09-16 | 1999-04-09 | Kyocera Corp | 多層配線基板 |
JP2000174052A (ja) * | 1998-09-30 | 2000-06-23 | Ibiden Co Ltd | 半導体チップ及び半導体チップの製造方法 |
JP2000200848A (ja) * | 1999-01-06 | 2000-07-18 | Shinko Electric Ind Co Ltd | 電子部品実装用回路基板及び半導体装置 |
JP2001168224A (ja) * | 1999-12-08 | 2001-06-22 | Sony Corp | 半導体装置、電子回路装置および製造方法 |
JP2001210953A (ja) * | 2000-01-27 | 2001-08-03 | Ngk Spark Plug Co Ltd | 配線基板及び配線基板の製造方法 |
JP2004047667A (ja) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | 多層配線基板およびその製造方法 |
Also Published As
Publication number | Publication date |
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JP2006080199A (ja) | 2006-03-23 |
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