JP4509972B2 - 配線基板、埋め込み用セラミックチップ - Google Patents
配線基板、埋め込み用セラミックチップ Download PDFInfo
- Publication number
- JP4509972B2 JP4509972B2 JP2006161700A JP2006161700A JP4509972B2 JP 4509972 B2 JP4509972 B2 JP 4509972B2 JP 2006161700 A JP2006161700 A JP 2006161700A JP 2006161700 A JP2006161700 A JP 2006161700A JP 4509972 B2 JP4509972 B2 JP 4509972B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- main surface
- layer
- ceramic
- terminal electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/236—Terminals leading through the housing, i.e. lead-through
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10712—Via grid array, e.g. via grid array capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006161700A JP4509972B2 (ja) | 2005-09-01 | 2006-06-09 | 配線基板、埋め込み用セラミックチップ |
| US11/508,968 US7557440B2 (en) | 2005-09-01 | 2006-08-24 | Wiring board and ceramic chip to be embedded |
| US12/475,648 US7956454B2 (en) | 2005-09-01 | 2009-06-01 | Wiring board and ceramic chip to be embedded |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005254031 | 2005-09-01 | ||
| JP2006161700A JP4509972B2 (ja) | 2005-09-01 | 2006-06-09 | 配線基板、埋め込み用セラミックチップ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007096262A JP2007096262A (ja) | 2007-04-12 |
| JP2007096262A5 JP2007096262A5 (enExample) | 2009-09-10 |
| JP4509972B2 true JP4509972B2 (ja) | 2010-07-21 |
Family
ID=37802920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006161700A Expired - Fee Related JP4509972B2 (ja) | 2005-09-01 | 2006-06-09 | 配線基板、埋め込み用セラミックチップ |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US7557440B2 (enExample) |
| JP (1) | JP4509972B2 (enExample) |
Families Citing this family (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7825522B2 (en) * | 2006-07-18 | 2010-11-02 | Lsi Corporation | Hybrid bump capacitor |
| KR100849791B1 (ko) * | 2007-03-12 | 2008-07-31 | 삼성전기주식회사 | 캐패시터 내장형 인쇄회로기판 |
| JP5394625B2 (ja) * | 2007-10-05 | 2014-01-22 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| JP2009099589A (ja) * | 2007-10-12 | 2009-05-07 | Elpida Memory Inc | ウエハまたは回路基板およびその接続構造体 |
| US8698278B2 (en) * | 2008-03-24 | 2014-04-15 | Ngk Spark Plug Co., Ltd. | Component-incorporating wiring board |
| JP5005599B2 (ja) * | 2008-03-31 | 2012-08-22 | Tdk株式会社 | 電子部品及び電子部品モジュール |
| JP5217584B2 (ja) * | 2008-04-07 | 2013-06-19 | 株式会社村田製作所 | 積層セラミック電子部品 |
| JP5185683B2 (ja) * | 2008-04-24 | 2013-04-17 | パナソニック株式会社 | Ledモジュールの製造方法および照明器具の製造方法 |
| US7745920B2 (en) | 2008-06-10 | 2010-06-29 | Micron Technology, Inc. | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
| JP5314370B2 (ja) * | 2008-09-16 | 2013-10-16 | 日本特殊陶業株式会社 | セラミック部品の製造方法 |
| JP2010087499A (ja) * | 2008-09-30 | 2010-04-15 | Ibiden Co Ltd | コンデンサ装置の製造方法 |
| TWI366906B (en) * | 2009-03-31 | 2012-06-21 | Ind Tech Res Inst | Die stacking structure and fabricating method thereof |
| JP5535765B2 (ja) * | 2009-06-01 | 2014-07-02 | 日本特殊陶業株式会社 | セラミックコンデンサの製造方法 |
| JP5524715B2 (ja) * | 2009-06-01 | 2014-06-18 | 日本特殊陶業株式会社 | セラミックコンデンサ、配線基板 |
| JPWO2011089936A1 (ja) * | 2010-01-22 | 2013-05-23 | 日本電気株式会社 | 機能素子内蔵基板及び配線基板 |
| TW201135980A (en) * | 2010-04-02 | 2011-10-16 | Icp Technology Co Ltd | Light-emitting diode with substrate having surrounding wall and manufacturing method thereof |
| JP5548060B2 (ja) * | 2010-07-28 | 2014-07-16 | 株式会社東芝 | 半導体装置 |
| TWI411073B (zh) * | 2010-08-13 | 2013-10-01 | 欣興電子股份有限公司 | 嵌埋被動元件之封裝基板及其製法 |
| TWI446497B (zh) * | 2010-08-13 | 2014-07-21 | 欣興電子股份有限公司 | 嵌埋被動元件之封裝基板及其製法 |
| US20120068218A1 (en) * | 2010-09-17 | 2012-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermally efficient packaging for a photonic device |
| JP2012104557A (ja) * | 2010-11-08 | 2012-05-31 | Ngk Spark Plug Co Ltd | 電子部品付き配線基板及びその製造方法 |
| JP2012216611A (ja) * | 2011-03-31 | 2012-11-08 | Sony Corp | 薄膜キャパシタ、実装基板およびその製造方法 |
| US10622310B2 (en) | 2012-09-26 | 2020-04-14 | Ping-Jung Yang | Method for fabricating glass substrate package |
| JP6144058B2 (ja) * | 2013-01-31 | 2017-06-07 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
| JP6013960B2 (ja) * | 2013-03-28 | 2016-10-25 | 京セラ株式会社 | 配線基板 |
| US9786434B2 (en) * | 2013-10-22 | 2017-10-10 | Samsung Electro-Mechanics Co., Ltd. | Multilayer ceramic electronic component and printed circuit board having the same |
| US9331021B2 (en) * | 2014-04-30 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-wafer package and method of forming same |
| JP2016076658A (ja) * | 2014-10-08 | 2016-05-12 | イビデン株式会社 | 電子部品内蔵配線板及びその製造方法 |
| US9601410B2 (en) | 2015-01-07 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
| US9627365B1 (en) * | 2015-11-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tri-layer CoWoS structure |
| US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
| JP2017123459A (ja) * | 2016-01-08 | 2017-07-13 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | プリント回路基板 |
| US9831148B2 (en) * | 2016-03-11 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package including voltage regulators and methods forming same |
| US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
| US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
| TW202431592A (zh) | 2016-12-29 | 2024-08-01 | 美商艾德亞半導體接合科技有限公司 | 具有整合式被動構件的接合結構 |
| WO2018169968A1 (en) | 2017-03-16 | 2018-09-20 | Invensas Corporation | Direct-bonded led arrays and applications |
| WO2018183739A1 (en) | 2017-03-31 | 2018-10-04 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
| US10510679B2 (en) | 2017-06-30 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with shield for electromagnetic interference |
| JP2019067858A (ja) * | 2017-09-29 | 2019-04-25 | イビデン株式会社 | プリント配線板及びその製造方法 |
| US11169326B2 (en) | 2018-02-26 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
| US11256004B2 (en) | 2018-03-20 | 2022-02-22 | Invensas Bonding Technologies, Inc. | Direct-bonded lamination for improved image clarity in optical devices |
| US11515291B2 (en) | 2018-08-28 | 2022-11-29 | Adeia Semiconductor Inc. | Integrated voltage regulator and passive components |
| CN109561570B (zh) * | 2018-11-21 | 2020-12-18 | 奥特斯(中国)有限公司 | 部件承载件及其制造方法以及使用填料颗粒的方法 |
| US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
| CN111834354B (zh) | 2019-04-18 | 2024-07-16 | 三星电子株式会社 | 半导体封装件 |
| JP7379899B2 (ja) * | 2019-07-22 | 2023-11-15 | Tdk株式会社 | セラミック電子部品 |
| JP7408975B2 (ja) * | 2019-09-19 | 2024-01-09 | Tdk株式会社 | セラミック電子部品 |
| US11762200B2 (en) | 2019-12-17 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded optical devices |
| CN113013125B (zh) * | 2019-12-20 | 2024-07-09 | 奥特斯奥地利科技与系统技术有限公司 | 嵌入有在侧向上位于堆叠体的导电结构之间的内插件的部件承载件 |
| US11705378B2 (en) * | 2020-07-20 | 2023-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages and methods of forming the same |
| WO2024252863A1 (ja) * | 2023-06-07 | 2024-12-12 | 株式会社村田製作所 | 積層セラミックコンデンサ |
| WO2024252864A1 (ja) * | 2023-06-07 | 2024-12-12 | 株式会社村田製作所 | 積層セラミックコンデンサ |
| US12347628B1 (en) * | 2024-08-27 | 2025-07-01 | Saras Micro Devices, Inc. | Stackable and embeddable vertical capacitors in semiconductor devices and method of fabrication |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3672169B2 (ja) * | 1999-03-05 | 2005-07-13 | 日本特殊陶業株式会社 | コンデンサ、コア基板本体の製造方法、及び、コンデンサ内蔵コア基板の製造方法 |
| JP3489728B2 (ja) * | 1999-10-18 | 2004-01-26 | 株式会社村田製作所 | 積層コンデンサ、配線基板および高周波回路 |
| JP2004172412A (ja) * | 2002-11-20 | 2004-06-17 | Kyocera Corp | コンデンサ素子およびコンデンサ素子内蔵多層配線基板 |
| JP2005039243A (ja) * | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 中間基板 |
| JP2005039217A (ja) | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 中間基板 |
| US7135534B2 (en) * | 2003-07-24 | 2006-11-14 | Rajiv Gandhi Centre For Biotechnology | Polymer support for solid phase peptide synthesis and process for preparation thereof |
| CN100367491C (zh) * | 2004-05-28 | 2008-02-06 | 日本特殊陶业株式会社 | 中间基板 |
| JP4528062B2 (ja) * | 2004-08-25 | 2010-08-18 | 富士通株式会社 | 半導体装置およびその製造方法 |
| TWI264094B (en) * | 2005-02-22 | 2006-10-11 | Phoenix Prec Technology Corp | Package structure with chip embedded in substrate |
-
2006
- 2006-06-09 JP JP2006161700A patent/JP4509972B2/ja not_active Expired - Fee Related
- 2006-08-24 US US11/508,968 patent/US7557440B2/en active Active
-
2009
- 2009-06-01 US US12/475,648 patent/US7956454B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7956454B2 (en) | 2011-06-07 |
| US20070045814A1 (en) | 2007-03-01 |
| US20090255719A1 (en) | 2009-10-15 |
| JP2007096262A (ja) | 2007-04-12 |
| US7557440B2 (en) | 2009-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4509972B2 (ja) | 配線基板、埋め込み用セラミックチップ | |
| US7932471B2 (en) | Capacitor for incorporation in wiring board, wiring board, method of manufacturing wiring board, and ceramic chip for embedment | |
| JP4838068B2 (ja) | 配線基板 | |
| JP5089880B2 (ja) | 配線基板内蔵用キャパシタ、キャパシタ内蔵配線基板及びその製造方法 | |
| JP5101240B2 (ja) | 板状部品内蔵配線基板 | |
| US7808799B2 (en) | Wiring board | |
| JP5112005B2 (ja) | 板状部品内蔵配線基板及びその製造方法 | |
| JP4954765B2 (ja) | 配線基板の製造方法 | |
| JP4964481B2 (ja) | 配線基板 | |
| JP5078759B2 (ja) | 配線基板内蔵用電子部品及び配線基板 | |
| JP4405477B2 (ja) | 配線基板及びその製造方法、埋め込み用セラミックチップ | |
| JP2007318089A (ja) | 配線基板 | |
| JP4648230B2 (ja) | 配線基板の製造方法 | |
| JP4668940B2 (ja) | 配線基板、埋め込み用セラミックチップ | |
| JP4405478B2 (ja) | 配線基板及びその製造方法、埋め込み用セラミックチップ | |
| JP2009004459A (ja) | コンデンサ内蔵配線基板 | |
| JP4975655B2 (ja) | 配線基板、半導体パッケージ | |
| JP2009147177A (ja) | 配線基板内蔵用コンデンサ及び配線基板 | |
| JP4814129B2 (ja) | 部品内蔵配線基板、配線基板内蔵用部品 | |
| JP4668822B2 (ja) | 配線基板の製造方法 | |
| JP4705867B2 (ja) | 配線基板の製造方法 | |
| JP2009004458A (ja) | コンデンサ内蔵配線基板及びその製造方法 | |
| JP5260067B2 (ja) | 配線基板、半導体パッケージ | |
| JP5395489B2 (ja) | 電子部品及びその製造方法、配線基板 | |
| JP2008270776A (ja) | 部品内蔵配線基板及びその製造方法、配線基板内蔵用コンデンサ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090319 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090723 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20090728 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20090805 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091127 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20091208 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100129 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100406 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100428 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4509972 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140514 Year of fee payment: 4 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |