JP4385324B2 - 半導体モジュールおよびその製造方法 - Google Patents
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- JP4385324B2 JP4385324B2 JP2004187035A JP2004187035A JP4385324B2 JP 4385324 B2 JP4385324 B2 JP 4385324B2 JP 2004187035 A JP2004187035 A JP 2004187035A JP 2004187035 A JP2004187035 A JP 2004187035A JP 4385324 B2 JP4385324 B2 JP 4385324B2
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
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- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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Description
まず、半導体モジュールの製作方法について説明する。図1に、本発明の実施形態にかかる半導体モジュールの製作方法と構造を示す。最初に、シリコンウエハ状態で所定の半導体回路を形成する(図1(a))。ここではパワー半導体であるIGBT素子の例を示している。シリコンウエハ25の上部にはエミッタ用電極21とゲート用電極22が形成される。通常、エミッタ用電極21、ゲート用電極22はアルミワイヤーボンデイングを施すのでAl−Si膜の上にAl膜を数μmの厚さに形成し用いる。ここでは、はんだをコートするため、はんだ付け用電極をさらに形成する必要がある。Al電極の上にTi、Ni、Auをスパッタもしくは蒸着により形成する。または、湿式メッキ法により直接Ni、Auをコートしてもよい。シリコンウエハ25下部はコレクタ電極用の裏面電極23を形成する。通常、スパッタによりシリコンウエハ25側より、Ti、Ni、AuもしくはTi、Ni、Agなどの膜を形成しはんだ付け用電極とする。
1b 下部用リードフレーム
2 パワー半導体
2b 駆動IC
3 駆動IC
4a パワー用ボンディングワイヤ
4b 信号用ボンディングワイヤ
5 成形樹脂
6 ヒートシンク
7 金属ベース基板
7a 上部用金属ベース基板
7c 下部用金属ベース基板
7b DBC基板
8 シリコーンゲル
9 ケース
21 エミッタ用電極
22 ゲート用電極
23 裏面電極
24 はんだ
Claims (6)
- ベース金属および前記ベース金属の上の絶縁層を有する上部金属ベース基板および下部金属ベース基板と、
前記上部金属ベース基板と前記下部金属ベース基板との間に鉛フリーはんだによりはんだ付けされた1または複数の回路素子と、
前記1または複数の回路素子と前記上部金属ベース基板および前記下部金属ベース基板との間の隙間に充填された樹脂と
を備える半導体モジュールであって、
前記上部金属ベース基板および前記下部金属ベース基板が有する前記絶縁層のヤング率は、500MPa〜5GPaの範囲であることを特徴とする半導体モジュール。 - 前記金属ベース基板の外周縁部分が樹脂封止により当該樹脂内に構成されていることを特徴とする請求項1に記載の半導体モジュール。
- 前記上部および下部金属ベース基板に各々接続されたリード端子が前記樹脂の成形部分の側面より取り出されていることを特徴する請求項1に記載の半導体モジュール。
- 前記樹脂は、熱伝導率が0.2〜10W/m・Kであることを特徴とする請求項1に記載の半導体モジュール。
- 前記金属ベース基板の絶縁層は、酸化珪素、酸化アルミニウム、窒化珪素、窒化アルミニウム、窒化ホウ素からなるフィラー群の1種類以上を含むことを特徴とする請求項1に記載の半導体モジュール。
- 1または複数の回路素子を、ベース金属および前記ベース金属の上の絶縁層を有する上部金属ベース基板および下部金属ベース基板の間にはんだ付けした半導体モジュールを製造する方法であって、
前記回路素子に、ウエハー段階で、鉛フリーはんだをコートする第1工程と、
前記コート後の回路素子を、前記上部金属ベース基板にはんだ付け接合する第2工程と、
前記回路素子が搭載された前記上部金属ベース基板を前記下部金属ベース基板に鉛フリーはんだによりはんだ付け接合する第3工程と、
前記第3工程後の前記回路素子と前記上部および下部金属ベース基板との間の隙間を成形樹脂により封止成形する第4工程と
を含み、
前記上部金属ベース基板および前記下部金属ベース基板が有する前記絶縁層のヤング率は、500MPa〜5GPaの範囲であることを特徴とする方法。
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JP2004187035A JP4385324B2 (ja) | 2004-06-24 | 2004-06-24 | 半導体モジュールおよびその製造方法 |
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JP2004187035A JP4385324B2 (ja) | 2004-06-24 | 2004-06-24 | 半導体モジュールおよびその製造方法 |
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JP2006013080A JP2006013080A (ja) | 2006-01-12 |
JP4385324B2 true JP4385324B2 (ja) | 2009-12-16 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018105486A1 (ja) | 2016-12-06 | 2018-06-14 | 株式会社 東芝 | 半導体装置 |
WO2019155659A1 (ja) | 2018-02-07 | 2019-08-15 | 株式会社 東芝 | 半導体装置 |
US10438932B2 (en) | 2016-08-08 | 2019-10-08 | Semiconductor Components Industries, Llc | Semiconductor device and method of integrating power module with interposer and opposing substrates |
WO2020070899A1 (ja) | 2018-10-05 | 2020-04-09 | 株式会社 東芝 | 半導体パッケージ |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007036214A (ja) * | 2005-06-21 | 2007-02-08 | Diamond Electric Mfg Co Ltd | 冷却構造および冷却装置 |
JP4961314B2 (ja) * | 2007-09-28 | 2012-06-27 | 日立オートモティブシステムズ株式会社 | パワー半導体装置 |
JP5239736B2 (ja) * | 2008-10-22 | 2013-07-17 | 株式会社デンソー | 電子装置 |
JP5549118B2 (ja) * | 2009-05-27 | 2014-07-16 | トヨタ自動車株式会社 | 半導体装置の製造方法 |
JP2011114176A (ja) * | 2009-11-27 | 2011-06-09 | Mitsubishi Electric Corp | パワー半導体装置 |
JP6475918B2 (ja) | 2014-02-05 | 2019-02-27 | ローム株式会社 | パワーモジュール |
DE102015208348B3 (de) * | 2015-05-06 | 2016-09-01 | Siemens Aktiengesellschaft | Leistungsmodul sowie Verfahren zum Herstellen eines Leistungsmoduls |
JP2018133448A (ja) | 2017-02-15 | 2018-08-23 | 株式会社東芝 | 半導体装置 |
JP6922450B2 (ja) * | 2017-06-08 | 2021-08-18 | 株式会社デンソー | 半導体モジュール |
EP3547367A1 (en) * | 2018-03-30 | 2019-10-02 | Mitsubishi Electric R&D Centre Europe B.V. | Power module incorporating pre-packed power cells |
JP6691984B2 (ja) * | 2019-02-04 | 2020-05-13 | ローム株式会社 | パワーモジュール |
CN111146096B (zh) * | 2019-11-26 | 2021-10-12 | 通富微电子股份有限公司 | 一种双面散热半导体器件及其单次回流的焊接方法 |
JP7447530B2 (ja) | 2020-02-17 | 2024-03-12 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
KR102477304B1 (ko) * | 2021-03-12 | 2022-12-13 | 파워마스터반도체 주식회사 | 양면 냉각 파워 모듈 패키지 |
CN116454028A (zh) * | 2023-06-14 | 2023-07-18 | 赛晶亚太半导体科技(浙江)有限公司 | 一种高效散热的igbt模块及其制备方法 |
-
2004
- 2004-06-24 JP JP2004187035A patent/JP4385324B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10438932B2 (en) | 2016-08-08 | 2019-10-08 | Semiconductor Components Industries, Llc | Semiconductor device and method of integrating power module with interposer and opposing substrates |
WO2018105486A1 (ja) | 2016-12-06 | 2018-06-14 | 株式会社 東芝 | 半導体装置 |
US11088118B2 (en) | 2016-12-06 | 2021-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
WO2019155659A1 (ja) | 2018-02-07 | 2019-08-15 | 株式会社 東芝 | 半導体装置 |
WO2020070899A1 (ja) | 2018-10-05 | 2020-04-09 | 株式会社 東芝 | 半導体パッケージ |
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