JP4322189B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4322189B2
JP4322189B2 JP2004255531A JP2004255531A JP4322189B2 JP 4322189 B2 JP4322189 B2 JP 4322189B2 JP 2004255531 A JP2004255531 A JP 2004255531A JP 2004255531 A JP2004255531 A JP 2004255531A JP 4322189 B2 JP4322189 B2 JP 4322189B2
Authority
JP
Japan
Prior art keywords
film
semiconductor device
connection pad
silicon oxide
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004255531A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006073805A (ja
JP2006073805A5 (enExample
Inventor
康弘 中
富生 岩▲崎▼
秀一 奥田
裕二 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004255531A priority Critical patent/JP4322189B2/ja
Priority to US11/172,207 priority patent/US20060043605A1/en
Publication of JP2006073805A publication Critical patent/JP2006073805A/ja
Publication of JP2006073805A5 publication Critical patent/JP2006073805A5/ja
Priority to US12/401,491 priority patent/US20090174061A1/en
Application granted granted Critical
Publication of JP4322189B2 publication Critical patent/JP4322189B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
    • H10W72/01255—Changing the shapes of bumps by using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
JP2004255531A 2004-09-02 2004-09-02 半導体装置 Expired - Fee Related JP4322189B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004255531A JP4322189B2 (ja) 2004-09-02 2004-09-02 半導体装置
US11/172,207 US20060043605A1 (en) 2004-09-02 2005-06-29 Semiconductor device
US12/401,491 US20090174061A1 (en) 2004-09-02 2009-03-10 Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004255531A JP4322189B2 (ja) 2004-09-02 2004-09-02 半導体装置

Publications (3)

Publication Number Publication Date
JP2006073805A JP2006073805A (ja) 2006-03-16
JP2006073805A5 JP2006073805A5 (enExample) 2006-11-24
JP4322189B2 true JP4322189B2 (ja) 2009-08-26

Family

ID=35941942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004255531A Expired - Fee Related JP4322189B2 (ja) 2004-09-02 2004-09-02 半導体装置

Country Status (2)

Country Link
US (2) US20060043605A1 (enExample)
JP (1) JP4322189B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4322189B2 (ja) * 2004-09-02 2009-08-26 株式会社ルネサステクノロジ 半導体装置
JP5162851B2 (ja) * 2006-07-14 2013-03-13 富士通セミコンダクター株式会社 半導体装置及びその製造方法
DE102007023590A1 (de) * 2007-05-21 2008-11-27 Epcos Ag Bauelement mit mechanisch belastbarer Anschlussfläche
US7919409B2 (en) * 2008-08-15 2011-04-05 Air Products And Chemicals, Inc. Materials for adhesion enhancement of copper film on diffusion barriers
WO2010092691A1 (ja) * 2009-02-16 2010-08-19 トヨタ自動車株式会社 半導体装置
CN104321860B (zh) * 2009-09-17 2017-06-06 皇家飞利浦电子股份有限公司 电子器件中易碎无机层处的接触部位的几何结构
DE102012109161B4 (de) * 2012-09-27 2021-10-28 Pictiva Displays International Limited Organisches, optoelektronisches Bauelement, Verfahren zum Herstellen eines organischen, optoelektronischen Bauelementes und Verfahren zum stoffschlüssigen, elektrischen Kontaktieren
US9245770B2 (en) * 2012-12-20 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of simultaneous molding and thermalcompression bonding
JP7629756B2 (ja) * 2021-03-03 2025-02-14 Tdk株式会社 積層電極、電極付き歪抵抗膜および圧力センサ
WO2023058201A1 (ja) * 2021-10-07 2023-04-13 Tdk株式会社 積層電極、電極付き歪抵抗膜および圧力センサ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6742248B2 (en) * 2001-05-14 2004-06-01 The Boeing Company Method of forming a soldered electrical connection
DE10308275A1 (de) * 2003-02-26 2004-09-16 Advanced Micro Devices, Inc., Sunnyvale Strahlungsresistentes Halbleiterbauteil
US20050104208A1 (en) * 2003-11-14 2005-05-19 International Business Machines Corporation Stabilizing copper overlayer for enhanced c4 interconnect reliability
US6951803B2 (en) * 2004-02-26 2005-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method to prevent passivation layer peeling in a solder bump formation process
US7064446B2 (en) * 2004-03-29 2006-06-20 Intel Corporation Under bump metallization layer to enable use of high tin content solder bumps
JP4322189B2 (ja) * 2004-09-02 2009-08-26 株式会社ルネサステクノロジ 半導体装置

Also Published As

Publication number Publication date
JP2006073805A (ja) 2006-03-16
US20090174061A1 (en) 2009-07-09
US20060043605A1 (en) 2006-03-02

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