JP4317576B2 - 自動生成されたダミー形状にもかかわらず整合する回路素子機能 - Google Patents

自動生成されたダミー形状にもかかわらず整合する回路素子機能 Download PDF

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Publication number
JP4317576B2
JP4317576B2 JP2007550384A JP2007550384A JP4317576B2 JP 4317576 B2 JP4317576 B2 JP 4317576B2 JP 2007550384 A JP2007550384 A JP 2007550384A JP 2007550384 A JP2007550384 A JP 2007550384A JP 4317576 B2 JP4317576 B2 JP 4317576B2
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pitch
pattern
circuit elements
dummy
dummy shape
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JP2008527712A5 (enExample
JP2008527712A (ja
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ランディス、ハワード、エス
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International Business Machines Corp
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18Manufacturability analysis or optimisation for manufacturability
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2007550384A 2005-01-06 2005-12-16 自動生成されたダミー形状にもかかわらず整合する回路素子機能 Expired - Fee Related JP4317576B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/905,474 US7269818B2 (en) 2005-01-06 2005-01-06 Circuit element function matching despite auto-generated dummy shapes
PCT/US2005/045787 WO2006073758A2 (en) 2005-01-06 2005-12-16 Circuit element function matching despite auto-generated dummy shapes

Publications (3)

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JP2008527712A JP2008527712A (ja) 2008-07-24
JP2008527712A5 JP2008527712A5 (enExample) 2008-10-09
JP4317576B2 true JP4317576B2 (ja) 2009-08-19

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JP2007550384A Expired - Fee Related JP4317576B2 (ja) 2005-01-06 2005-12-16 自動生成されたダミー形状にもかかわらず整合する回路素子機能

Country Status (5)

Country Link
US (2) US7269818B2 (enExample)
EP (1) EP1846851A4 (enExample)
JP (1) JP4317576B2 (enExample)
CN (1) CN101099154B (enExample)
WO (1) WO2006073758A2 (enExample)

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JP2009053763A (ja) * 2007-08-23 2009-03-12 Nec Electronics Corp ダミーパターン配置装置、ダミーパターン配置方法
CN102445864A (zh) * 2011-10-21 2012-05-09 上海华力微电子有限公司 一种降低光刻对准失效率的方法
US8739078B2 (en) * 2012-01-18 2014-05-27 International Business Machines Corporation Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications
JP6205831B2 (ja) * 2012-07-04 2017-10-04 株式会社ソシオネクスト マスクパターン生成方法、マスクパターン生成装置、及び、マスクパターン生成プログラム

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Also Published As

Publication number Publication date
US7269818B2 (en) 2007-09-11
US20080022248A1 (en) 2008-01-24
WO2006073758A2 (en) 2006-07-13
EP1846851A4 (en) 2009-11-04
US20060150139A1 (en) 2006-07-06
US7721248B2 (en) 2010-05-18
WO2006073758A3 (en) 2007-03-01
CN101099154B (zh) 2012-12-12
EP1846851A2 (en) 2007-10-24
CN101099154A (zh) 2008-01-02
JP2008527712A (ja) 2008-07-24

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