JP4314105B2 - 薄膜トランジスタ液晶表示装置の製造方法 - Google Patents
薄膜トランジスタ液晶表示装置の製造方法 Download PDFInfo
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- JP4314105B2 JP4314105B2 JP2003403812A JP2003403812A JP4314105B2 JP 4314105 B2 JP4314105 B2 JP 4314105B2 JP 2003403812 A JP2003403812 A JP 2003403812A JP 2003403812 A JP2003403812 A JP 2003403812A JP 4314105 B2 JP4314105 B2 JP 4314105B2
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- 239000010409 thin film Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 21
- 238000000034 method Methods 0.000 title claims description 16
- 230000008021 deposition Effects 0.000 claims description 71
- 239000010408 film Substances 0.000 claims description 42
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 34
- 238000007740 vapor deposition Methods 0.000 claims description 15
- 230000001681 protective effect Effects 0.000 claims description 7
- 238000005086 pumping Methods 0.000 claims description 4
- 230000002040 relaxant effect Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 description 49
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
Description
110 ゲート電極
120 絶縁層
120a 第1絶縁膜
120b 第2絶縁膜
130 アクティブ層
130a 第1非晶質シリコン層
130b 第2非晶質シリコン層
140 オーミックコンタクト層
150 ソース/ドレイン電極
160 保護膜
Claims (8)
- 絶縁基板上にゲート電極を形成する段階と、
前記ゲート電極を含んだ絶縁基板上部に、ある一定のパワー、圧力、及び電極間隔による第1蒸着条件下で第1絶縁膜を形成した後、前記第1蒸着条件の内、少なくとも一つ以上の条件を連続的に第2蒸着条件へ変化させ第2絶縁膜を形成することによって前記第1蒸着条件から前記第2蒸着条件へ唐突に変化した場合よりも前記絶縁基板へのストレスを緩和させる段階と、
前記第2絶縁膜の上部に、ある一定のパワー、圧力、及び電極間隔による第3蒸着条件下で、第1非晶質シリコン層を形成した後、前記第3蒸着条件の内、少なくとも一つ以上の条件を連続的に第4蒸着条件へ変化させ第2非晶質シリコン層を形成することによって前記第3蒸着条件から前記第4蒸着条件へ唐突に変化した場合よりも前記絶縁基板へのストレスを緩和させてアクティブ層を形成する段階と、
前記アクティブ層の上部にオーミックコンタクト層とソース/ドレイン電極とを順次に形成する段階と、
前記ソース/ドレイン電極を含んだ結果構造物の上部に保護膜を形成する段階とを含んで構成されることを特徴とする薄膜トランジスタ液晶表示装置の製造方法。
- 前記第2絶縁膜の蒸着時に適用する第2蒸着条件の内、パワー、電極間隔、及び圧力のうち少なくとも一つ以上の条件を前記第1蒸着条件であるパワー、電極間隔、及び圧力の条件より小さく使用することを特徴とする請求項1に記載の薄膜トランジスタ液晶表示装置の製造方法。
- 前記第2蒸着条件の電極間隔は、モーターの回転速度を調節して連続的に変化させ、前記第2蒸着条件の圧力はポンプのポンピング速度を調節して連続的に変化させることを特徴とする請求項1又は2に記載の薄膜トランジスタ液晶表示装置の製造方法。
- 前記第2蒸着条件の電極間隔は1000milから600milに連続的に変化させ、前記第2蒸着条件の圧力は1700mTorrから1200mTorrに連続的に変化させることを特徴とする請求項1又は2に記載の薄膜トランジスタ液晶表示装置の製造方法。
- 前記第4蒸着条件下のパワーは100Wから600Wに連続的に変化させることを特徴とする請求項1に記載の薄膜トランジスタ液晶表示装置の製造方法。
- 絶縁基板上にゲート電極を形成する段階と、
前記ゲート電極を含んだ絶縁基板上部に、ある一定の圧力、及び電極間隔による第1蒸着条件下で第1絶縁膜を形成した後、前記第1蒸着条件の内、少なくとも一つ以上の条件を連続的に第2蒸着条件へ変化させ第2絶縁膜を形成することによって前記第1蒸着条件から前記第2蒸着条件へ唐突に変化した場合よりも前記絶縁基板へのストレスを緩和させる段階と、
前記第2絶縁膜の上部に、ある一定の圧力、及び電極間隔による第3蒸着条件下で、第1非晶質シリコン層を形成した後、前記第3蒸着条件の内、少なくとも一つ以上の条件を連続的に第4蒸着条件へ変化させ第2非晶質シリコン層を形成することによって前記第3蒸着条件から前記第4蒸着条件へ唐突に変化した場合よりも前記絶縁基板へのストレスを緩和させてアクティブ層を形成する段階と、
前記アクティブ層の上部にオーミックコンタクト層とソース/ドレイン電極とを順次に形成する段階と、
前記ソース/ドレイン電極を含んだ結果構造物の上部に保護膜を形成する段階とを含んで構成されることを特徴とする薄膜トランジスタ液晶表示装置の製造方法。
- 前記第2蒸着条件の電極間隔はモーターの回転速度を調節して連続的に変化させ、前記第2蒸着条件の圧力はポンプのポンピング速度を調節して連続的に変化させることを特徴とする請求項6に記載の薄膜トランジスタ液晶表示装置の製造方法。
- 前記第2蒸着条件の電極間隔は1000milから600milに連続的に変化させ、前記第2蒸着条件の圧力は1700mTorrから1200mTorrに連続的に変化させることを特徴とする請求項6に記載の薄膜トランジスタ液晶表示装置の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020030019956A KR100683149B1 (ko) | 2003-03-31 | 2003-03-31 | 액정표시소자용 어레이기판의 스트레스 제거방법 |
Publications (2)
Publication Number | Publication Date |
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JP2004304156A JP2004304156A (ja) | 2004-10-28 |
JP4314105B2 true JP4314105B2 (ja) | 2009-08-12 |
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JP2003403812A Expired - Lifetime JP4314105B2 (ja) | 2003-03-31 | 2003-12-02 | 薄膜トランジスタ液晶表示装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6841428B2 (ja) |
JP (1) | JP4314105B2 (ja) |
KR (1) | KR100683149B1 (ja) |
CN (1) | CN100356259C (ja) |
TW (1) | TWI255045B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI249251B (en) * | 2004-11-22 | 2006-02-11 | Au Optronics Corp | Fabrication method of thin film transistor |
KR100671824B1 (ko) * | 2005-12-14 | 2007-01-19 | 진 장 | 역 스태거드 박막 트랜지스터 제조 방법 |
CN100466266C (zh) * | 2006-04-21 | 2009-03-04 | 北京京东方光电科技有限公司 | 一种tft lcd阵列基板及制造方法 |
TWI641897B (zh) | 2006-05-16 | 2018-11-21 | 日商半導體能源研究所股份有限公司 | 液晶顯示裝置 |
JP2009099636A (ja) * | 2007-10-15 | 2009-05-07 | Hitachi Displays Ltd | 表示装置および表示装置の製造方法 |
WO2009129391A2 (en) * | 2008-04-17 | 2009-10-22 | Applied Materials, Inc. | Low temperature thin film transistor process, device property, and device stability improvement |
TWI500159B (zh) * | 2008-07-31 | 2015-09-11 | Semiconductor Energy Lab | 半導體裝置和其製造方法 |
CN104795449B (zh) | 2015-04-16 | 2016-04-27 | 京东方科技集团股份有限公司 | 薄膜晶体管及制作方法、阵列基板、显示装置 |
CN107146792B (zh) * | 2017-05-11 | 2019-07-30 | 京东方科技集团股份有限公司 | 一种静电防护装置及其制作方法 |
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JP3288615B2 (ja) * | 1997-10-21 | 2002-06-04 | 株式会社アドバンスト・ディスプレイ | 薄膜トランジスタの製造方法 |
KR100386848B1 (ko) * | 2001-05-09 | 2003-06-09 | 엘지.필립스 엘시디 주식회사 | 박막 트랜지스터 표시소자의 반도체층 재생방법 |
TW541584B (en) * | 2001-06-01 | 2003-07-11 | Semiconductor Energy Lab | Semiconductor film, semiconductor device and method for manufacturing same |
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2003
- 2003-03-31 KR KR1020030019956A patent/KR100683149B1/ko active IP Right Grant
- 2003-11-25 US US10/722,275 patent/US6841428B2/en not_active Expired - Lifetime
- 2003-11-26 TW TW092133149A patent/TWI255045B/zh not_active IP Right Cessation
- 2003-12-02 JP JP2003403812A patent/JP4314105B2/ja not_active Expired - Lifetime
- 2003-12-24 CN CNB200310123510XA patent/CN100356259C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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US6841428B2 (en) | 2005-01-11 |
TWI255045B (en) | 2006-05-11 |
US20040191969A1 (en) | 2004-09-30 |
TW200421623A (en) | 2004-10-16 |
JP2004304156A (ja) | 2004-10-28 |
CN100356259C (zh) | 2007-12-19 |
CN1534361A (zh) | 2004-10-06 |
KR100683149B1 (ko) | 2007-02-15 |
KR20040085313A (ko) | 2004-10-08 |
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