WO2019041934A1 - 电极结构及其制作方法、薄膜晶体管和阵列基板 - Google Patents

电极结构及其制作方法、薄膜晶体管和阵列基板 Download PDF

Info

Publication number
WO2019041934A1
WO2019041934A1 PCT/CN2018/089632 CN2018089632W WO2019041934A1 WO 2019041934 A1 WO2019041934 A1 WO 2019041934A1 CN 2018089632 W CN2018089632 W CN 2018089632W WO 2019041934 A1 WO2019041934 A1 WO 2019041934A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
protective layer
conductive layer
metal
protective
Prior art date
Application number
PCT/CN2018/089632
Other languages
English (en)
French (fr)
Inventor
王东方
袁广才
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201721104937.9U external-priority patent/CN207068871U/zh
Priority claimed from CN201710769888.9A external-priority patent/CN107507868A/zh
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/326,256 priority Critical patent/US20200403102A1/en
Publication of WO2019041934A1 publication Critical patent/WO2019041934A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • Embodiments of the present disclosure relate to the field of display technologies, and in particular, to an electrode structure and a method of fabricating the same, a thin film transistor, and an array substrate.
  • the thin film transistor TFT may include an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source/drain electrode, and a passivation layer.
  • the surface of the electrode structure is prone to bubbles or even cracks, thereby affecting the conductivity and lowering the yield of the thin film transistor.
  • an electrode structure comprising: an electrical conductor including a protective layer and a conductive layer; the protective layer comprising: a first protective layer disposed on a surface of the conductive layer and disposed at a side of at least the conductive layer a second protective layer for isolating the conductive layer from the outside.
  • the materials of the first protective layer and the second protective layer are different.
  • the second protective layer can be used to block oxygen and/or hydrogen.
  • the first protective layer includes: a first metal layer disposed on a side of the conductive layer adjacent to the substrate, and a second metal layer disposed on the conductive layer Keep away from the side of the substrate.
  • the second protective layer is disposed to cover a side of the conductive layer, and the height of the second protective layer is substantially equal to a thickness of the conductive layer. In one embodiment, the second protective layer is disposed to completely cover the sides of the conductive layer.
  • the second protective layer is disposed to cover sides of the first metal layer, the conductive layer, and the second metal layer, the second protective layer having a height substantially equal to the first metal layer The sum of the thicknesses of the conductive layer and the second metal layer.
  • the material of the conductive layer comprises aluminum and the material of the second protective layer comprises aluminum nitride. In one embodiment, the materials of the first metal layer and the second metal layer are different.
  • the second protective layer has a thickness of 5 to 50 nanometers.
  • the materials of the first metal layer and the second metal layer include: molybdenum (Mo).
  • the conductive layer comprises a metallic material.
  • a thin film transistor which may include the electrode structure according to any of the embodiments, the conductor being at least one of the following of the thin film transistor: a gate electrode, a source electrode, Leakage electrode, or wiring.
  • an array substrate that includes a thin film transistor of any of the aspects or embodiments described above.
  • a method of fabricating an electrode structure comprising: forming a conductive layer and a first protective layer for a conductive layer on a substrate; and forming a second protective layer, the second protective layer being at least Covering the side of the conductive layer, the second protective layer is used to isolate the conductive layer from the outside.
  • the materials of the first protective layer and the second protective layer are different.
  • the second protective layer is used to block oxygen and/or hydrogen.
  • the forming a conductive layer on the substrate and the first protective layer disposed on the surface of the conductive layer includes: forming a laminate of the first metal film, the conductive film, and the second metal film on the substrate; The layer is patterned to form a first metal layer, the conductive layer and a second metal layer, wherein the first protective layer comprises: a first metal layer and a second metal layer.
  • forming the second protective layer comprises treating the conductive layer with nitrogen plasma to form the second protective layer.
  • forming the second protective layer includes: depositing a protective material film on the substrate on which the first metal layer, the conductive layer, and the second metal layer are formed, the protective material film covering at least the second metal layer and a side surface of the first metal layer, the conductive layer, and the second metal layer; a portion of the protective material film on a side of the first metal layer, the conductive layer, and the second metal layer is retained by a patterning process, thereby forming the Second protective layer.
  • the electrical conductor is at least one of the following: a gate electrode, a source electrode, a drain electrode, or a wiring.
  • the conductive film is formed of a metal material.
  • FIG. 1 is a simplified schematic diagram of a conventional thin film transistor
  • FIG. 2 is a schematic structural diagram of an electrode according to some embodiments of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic structural diagram of an electrode according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure.
  • FIG. 6 is a flow chart of a method of fabricating a thin film transistor according to some embodiments of the present disclosure
  • 6A is a schematic diagram of a method of fabricating a thin film transistor according to some embodiments of the present disclosure
  • 6B is a schematic diagram of a method of fabricating a thin film transistor according to some embodiments of the present disclosure
  • 6C is a schematic diagram of a method of fabricating a thin film transistor according to some embodiments of the present disclosure.
  • 6D is a schematic diagram of a method of fabricating a thin film transistor according to some embodiments of the present disclosure.
  • FIG. 7A is a schematic diagram of a method of fabricating a thin film transistor according to some embodiments of the present disclosure.
  • FIG. 7B is a schematic diagram of a method of fabricating a thin film transistor according to some embodiments of the present disclosure.
  • FIG. 1 is a simplified schematic diagram of a conventional thin film transistor.
  • an electrode is formed on the substrate 1, and an insulating layer 5 made of silicon oxide is disposed on the electrode.
  • the electrode comprises: a first layer 2 of molybdenum material 2, a second layer 3 of material aluminum and a third layer 4 of material molybdenum.
  • the electrode is a gate electrode or a source/drain electrode.
  • the insulating layer may be an interlayer insulating layer in the top gate structure, and the insulating layer may be a gate insulating layer in the bottom gate structure.
  • the insulating layer may be a passivation layer.
  • the edge portion of the second layer 3 is oxidized to form aluminum oxide before or during the formation of the insulating layer 5. Therefore, after the insulating layer 5 is formed, the alumina of the edge of the second layer 3 is brought into contact with the silicon oxide.
  • the inventors have found that after the thin film transistor is fabricated, it is usually required to be placed in a high-temperature and high-humidity environment for reliability evaluation.
  • hydrogen atoms may always be present in the silicon oxide in a high temperature and high humidity environment.
  • the "walking" hydrogen atoms have enough space to form hydrogen molecules and put pressure on the surface of the metal aluminum.
  • the diameter of the pit is large to a certain critical size, the surface of the metal aluminum is plastically deformed and bulged outward to form bubbles.
  • the bubble density is sufficiently large, the surface of the metal aluminum forming the bubble may be broken, resulting in uneven contact resistance of the second layer or even metal breakage of the second layer, which seriously affects the conductivity of the electrode and reduces the yield of the thin film transistor.
  • the oxide film protective layer on the electrode will fall off, eventually leading to failure.
  • FIG. 2 is a schematic structural diagram of an electrode according to some embodiments of the present disclosure
  • FIG. 3 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure.
  • the thin film transistor includes a gate electrode 23 and a source/drain electrode 25.
  • the gate electrode 23 and/or the source/drain electrode 25 are electrodes including a protective layer and a conductive layer 10.
  • the protective layer includes: first protective layers (11 and 12) disposed on the surface of the conductive layer 10 and a second protective layer 13 disposed on the side of the conductive layer 10, the second protective layer 13 for isolating the conductive layer from the outside.
  • the second protective layer 13 can block the conductive layer from the silicon oxide.
  • the thin film transistor further includes an active layer 21, a gate insulating layer 22, an interlayer insulating layer 24, and a passivation layer 26 disposed on the substrate 20, as shown in FIG.
  • the structure of the thin film transistor may be a top gate structure or a bottom gate structure.
  • FIG. 3 is an example of a top gate structure.
  • FIG. 3 also illustrates an example in which the gate electrode and the source and drain electrodes are both provided by the embodiments of the present disclosure. It should also be understood herein that the principles of embodiments of the present disclosure may be applied to a wide variety of devices including, but not limited to, semiconductor devices, active devices such as transistors, and passive devices and the like.
  • the first protective layer includes: a first metal layer 11 disposed on the lower surface of the conductive layer 10 adjacent to the substrate 20, and a second metal layer 12 disposed on the conductive layer 10 away from the substrate The upper surface of 20.
  • the orthographic projection of the first metal layer 11 on the substrate 20 is greater than or equal to the orthographic projection of the conductive layer 10 on the substrate 20, and the conductive layer 10 is on the substrate 20.
  • the positive projection on the upper side is greater than or equal to the orthographic projection of the second metal layer 12 on the substrate 20.
  • the shape of the conductive layer 10 may be a prismatic or prismatic structure, or may also be a truncated cone or a cylindrical structure.
  • the shapes of the first metal layer 11 and the second metal layer 12 are the same as those of the conductive layer 10. Embodiments of the present disclosure are not limited to the embodiments shown or described herein.
  • the second protective layer 13 is disposed on the side of the conductive layer 10, and the height h of the second protective layer 13 is equal to the thickness of the conductive layer 10.
  • 10 close to the lower surface of the base 10 of the length l of the second protective layer 13 adjacent to the lower surface of the substrate 20 is twice the length l 1 of the conductive layer 2 is less than or equal to the first
  • the metal layer 11 is away from the length of the upper surface of the substrate 20. It is obvious that the present disclosure is not limited to.
  • the materials of the first protective layer and the second protective layer are different. Additionally, in some embodiments, the second protective layer can be disposed to completely cover the sides of the conductive layer.
  • the material of the first metal layer 11 and the second metal layer 12 includes molybdenum. It should be noted that the first metal layer 11 and the second metal layer 12 can not only be electrically conductive, but also can protect the conductive layer 10 from being oxidized. In some embodiments, the materials of the first metal layer and the second metal layer may be different.
  • the conductive layer 10 may be formed of a metal material.
  • the material of the conductive layer 10 includes: aluminum.
  • the material of the second protective layer 13 comprises: aluminum nitride. It should be noted that the second protective layer 13 may also be other materials having weak hydrogen permeability. The present disclosure is not limited to the embodiments shown or described herein.
  • the shape of the second protective layer 13 is related to the shape of the conductive layer 10.
  • the shape of the conductive layer 10 is a prism or a prism
  • the shape of the cross section of the second protective layer 13 is a parallelogram.
  • the shape of the conductive layer 10 is a truncated cone or a cylinder
  • the cross section of the second protective layer 13 has a rectangular shape. The present disclosure is not limited to the embodiments shown or described herein.
  • the second protective layer 13 has a thickness of about 5 to 50 nanometers.
  • the thin film transistor provided by the embodiment of the present disclosure may include: a gate electrode and a source/drain electrode, the gate electrode and/or the source/drain electrode are electrodes including a protective layer and a conductive layer, and the protective layer includes: a first protective layer disposed on a surface of the conductive layer And a second protective layer disposed on a side of the conductive layer, the second protective layer being used to isolate the conductive layer from the outside.
  • the second protective layer can be used to block oxygen and/or hydrogen.
  • a metal/metal oxide interface for example, an aluminum/alumina interface
  • oxidation of the conductive layer thereby avoiding hydrogen entering such an interface.
  • the contact resistance of the electrode due to hydrogen is uneven or even broken, and the crack of the protective film is avoided, thereby improving the conductivity of the conductor such as the electrode in the device, and improving the yield and reliability of the device.
  • FIG. 4 is a schematic structural diagram of an electrode according to some embodiments of the present disclosure
  • FIG. 5 is a schematic structural diagram of a thin film transistor according to some embodiments of the present disclosure.
  • the thin film transistor includes a gate electrode 23 and source/drain electrodes 25.
  • the gate electrode 23 and/or the source/drain electrode 25 are electrodes including a protective layer and a conductive layer 10, including: a first protective layer disposed on a surface of the conductive layer 10 and a second protective layer 13 disposed on a side of the conductive layer 10, and a second The protective layer 13 serves to isolate the conductive layer from the outside (for example, external silicon oxide or the like).
  • the materials of the first protective layer and the second protective layer are different.
  • the second protective layer is used to block oxygen and/or hydrogen.
  • the thin film transistor further includes an active layer 21, a gate insulating layer 22, an interlayer insulating layer 24, and a passivation layer 26 which are disposed on the substrate 20.
  • the structure of the thin film transistor may be a top gate structure or a bottom gate structure.
  • FIG. 5 is an example in which the top gate structure is taken as an example.
  • FIG. 5 also illustrates an example in which the gate electrode and the source and drain electrodes are both provided by the embodiments of the present disclosure.
  • the first protective layer includes: a first metal layer 11 disposed on the lower surface of the conductive layer 10 adjacent to the substrate 20, and a second metal layer 12 disposed on the conductive layer 10 away from the substrate The upper surface of 20. It is to be understood that the orthographic projection of the first metal layer 11 on the substrate 20 is greater than or equal to the orthographic projection of the conductive layer 10 on the substrate 20, and the orthographic projection of the conductive layer 10 on the substrate 20 is greater than or equal to the second metal layer 12 being An orthographic projection on the substrate 20.
  • the shape of the conductive layer 10 may be a prismatic or prismatic structure, or may also be a truncated cone or a cylindrical structure.
  • the shapes of the first metal layer 11 and the second metal layer 12 are the same as the shape of the conductive layer 10, and embodiments of the present disclosure are not limited to the embodiments shown or described herein.
  • the second protective layer 13 is disposed on the side surfaces of the first metal layer 11, the conductive layer 10, and the second metal layer 12.
  • the height h of the second protective layer 13 is equal to the sum of the thicknesses of the first metal layer 11, the conductive layer 10, and the second metal layer 12.
  • materials of the first metal layer 11 and the second metal layer 12 include, but are not limited to, molybdenum. It should be noted that the first metal layer 11 and the second metal layer 12 can be used not only to conduct electricity, but also to protect the conductive layer 10 from being oxidized.
  • the conductive layer 10 may be formed of a metal material.
  • the material of the conductive layer 10 includes: aluminum.
  • the material of the second protective layer 13 comprises: aluminum nitride. It should be noted that the second protective layer 13 may also be other materials whose hydrogen permeability is weak, and the disclosure is not limited to the embodiments shown or described herein.
  • the shape of the second protective layer 13 is related to the shape of the conductive layer.
  • the shape of the conductive layer is a prism or a prism
  • the shape of the cross section of the second protective layer 13 is a parallelogram.
  • the shape of the conductive layer is a truncated cone or a cylinder
  • the cross section of the second protective layer 13 has a rectangular shape. The present disclosure is not limited to the embodiments shown or described herein.
  • the second protective layer 13 has a thickness of about 5 to 50 nanometers.
  • a thin film transistor provided by an embodiment of the present disclosure includes: a gate electrode and a source/drain electrode, the gate electrode and/or the source/drain electrode is an electrode including a protective layer and a conductive layer, and the protective layer includes: a first protective layer disposed on a surface of the conductive layer; A second protective layer disposed on a side of the conductive layer.
  • the second protective layer serves to block oxygen and/or hydrogen.
  • FIG. 6 is a flow chart of a method of fabricating a thin film transistor according to some embodiments of the present disclosure. As shown in FIG. 6, the manufacturing method specifically includes the following steps:
  • Step S1 forming a conductive layer on the substrate and a first protective layer disposed on the surface of the conductive layer.
  • step S1 specifically includes:
  • Step S11 a stack of the first metal thin film, the conductive thin film and the second metal thin film is sequentially formed (for example, deposited) on the substrate.
  • the first metal film, the conductive film, and the second metal film may be deposited by a chemical vapor deposition (CVD) process, an evaporation process, or a sputtering process.
  • CVD chemical vapor deposition
  • evaporation process evaporation process
  • sputtering process evaporation process
  • the materials of the first metal film and the second metal film are each, for example, molybdenum.
  • the conductive film may be formed of a metal material such as aluminum.
  • Step S12 forming a first metal layer, a conductive layer and a second metal layer by a patterning process.
  • the laminate can be patterned to form a first metal layer, a conductive layer, and a second metal layer corresponding to the film in the laminate.
  • the patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping.
  • the first protective layer includes: a first metal layer and a second metal layer.
  • the orthographic projection of the first metal layer on the substrate is greater than or equal to the orthographic projection of the conductive layer on the substrate
  • the orthographic projection of the conductive layer on the substrate is greater than or equal to the orthographic projection of the second metal layer on the substrate.
  • the shape of the conductive layer may be a prismatic or prismatic structure, or may also be a truncated cone or a cylindrical structure.
  • the shapes of the first metal layer and the second metal layer are the same in the shape of the conductive layer. Embodiments of the present disclosure are not limited to the embodiments shown or described herein.
  • Step S2 forming a second protective layer on a side of the conductive layer to form an electrode including a protective layer and a conductive layer.
  • the protective layer comprises: a first protective layer and a second protective layer, wherein the second protective layer is used for isolating the conductive layer from the outside, for example, the conductive layer is in contact with the silicon oxide.
  • step S2 specifically includes: treating the conductive layer with nitrogen plasma to form a second protective layer disposed on a side of the conductive layer.
  • the material of the second protective layer is aluminum nitride.
  • the second protective layer may have a thickness of 5 to 50 nm. It should be noted that the thickness of the second protective layer can be controlled by the content of nitrogen. The present disclosure is not limited to the embodiments shown or described herein.
  • the process is simplified by using nitrogen plasma treatment, the mask is avoided, the complexity of the fabrication process is reduced, and the fabrication process of the thin film transistor is simplified.
  • the electrodes may be gate electrodes and/or source and drain electrodes.
  • a method for fabricating a thin film transistor includes: forming a conductive layer on a substrate and a first protective layer disposed on a surface of the conductive layer, and forming a second protective layer on a side of the conductive layer to form a protective layer and a conductive layer.
  • the electrode wherein the protective layer comprises: a first protective layer and a second protective layer, the second protective layer is used to isolate the conductive layer from the outside.
  • the second protective layer can be used to block oxygen and/or hydrogen.
  • a thin film transistor of a top gate structure, and a gate electrode and a source/drain electrode simultaneously including a conductive layer and a protective layer are taken as an example to further specifically describe a thin film transistor fabrication method provided by some embodiments of the present disclosure.
  • the patterning process includes: photoresist coating, exposure, development, etching, photoresist stripping and the like.
  • Step 101 forming an active layer 21 and a gate insulating layer 22 on the substrate 20, as shown in FIG. 6A.
  • the material of the substrate 20 may be, for example, glass or plastic.
  • the embodiment of the present disclosure does not have any particular limitation on the substrate, and those skilled in the art can also select the substrate according to actual needs.
  • the substrate 20 may be subjected to a pre-cleaning operation before the formation of the active layer 21.
  • the material of the active layer 21 is polysilicon.
  • the present disclosure is not limited to this.
  • the active layer 21 may be formed of any suitable semiconductor material such as, but not limited to, an oxide semiconductor such as silicon, such as IGZO.
  • the material of the gate insulating layer 22 may be silicon oxide and/or silicon nitride.
  • Step 102 depositing a first metal film 110, a conductive film 120, and a second metal film 130 on the substrate 20 on which the active layer 21 and the gate insulating layer 22 are formed, as shown in FIG. 6B.
  • the first metal film 110, the conductive film 120, and the second metal film 130 are deposited by a CVD process, an evaporation process, or a sputtering process.
  • the material of the first metal film 110 and the second metal film 130 is molybdenum, and the material of the conductive film 120 is aluminum.
  • Step 103 The first metal film 110, the conductive film 120, and the second metal film 130 are processed by a patterning process to form a first metal layer 11, a conductive layer 10, and a second metal layer 12, as shown in FIG. 6C.
  • the first protective layer includes a first metal layer 11 and a second metal layer 12.
  • Step 104 The conductive layer 10 is treated with nitrogen plasma to form a second protective layer 13 disposed on the side of the conductive layer 10 to form a gate electrode 23 including a protective layer and a conductive layer, as shown in FIG. 6D.
  • the protective layer includes a first metal layer 11 , a second metal layer 12 , and a second protective layer 13 .
  • Step 105 forming an interlayer insulating layer 24, a source/drain electrode 25, and a passivation layer 26 on the substrate 20, as shown in FIG.
  • the material of the interlayer insulating layer 24 and the passivation layer 26 is silicon oxide.
  • the source-drain electrodes 25 are formed by the processes of steps 102-104, and are not described herein again.
  • Some embodiments of the present disclosure provide a method for fabricating a thin film transistor, and the manufacturing method specifically includes the following steps:
  • Step S1 forming a conductive layer on the substrate and a first protective layer disposed on the surface of the conductive layer.
  • step S1 specifically includes:
  • Step S11 depositing a first metal thin film, a conductive thin film and a second metal thin film on the substrate in this order.
  • the first metal film, the conductive film, and the second metal film are deposited by a chemical vapor deposition (CVD) process, an evaporation process, or a sputtering process.
  • CVD chemical vapor deposition
  • evaporation process evaporation process
  • sputtering process evaporation process
  • the materials of the first metal film and the second metal film are both molybdenum, and the material of the conductive film is aluminum.
  • Step S12 forming a first metal layer, a conductive layer and a second metal layer by a patterning process.
  • the patterning process includes: photoresist coating, exposure, development, etching, and photoresist stripping.
  • the first protective layer includes a first metal layer and a second metal layer.
  • the orthographic projection of the first metal layer on the substrate is greater than or equal to the orthographic projection of the conductive layer on the substrate
  • the orthographic projection of the conductive layer on the substrate is greater than or equal to the orthographic projection of the second metal layer on the substrate.
  • the shape of the conductive layer may be a prismatic or prismatic structure, or may also be a truncated cone or a cylindrical structure.
  • the shapes of the first metal layer and the second metal layer are the same in the shape of the conductive layer. Embodiments of the present disclosure are not limited to the embodiments shown or described herein.
  • Step S2 forming a second protective layer on a side of the conductive layer to form an electrode including a protective layer and a conductive layer.
  • the protective layer comprises: a first protective layer and a second protective layer, wherein the second protective layer is used to isolate the conductive layer from the outside.
  • step S2 specifically includes:
  • Step S21 depositing a protective material film on the substrate on which the first metal layer, the conductive layer and the second metal layer are formed.
  • the protective material film is deposited by a chemical vapor deposition (CVD) process, an evaporation process, or a sputtering process.
  • CVD chemical vapor deposition
  • evaporation process evaporation process
  • sputtering process evaporation process
  • the material of the protective material film may be aluminum nitride.
  • the thickness of the protective material film may be 5 to 50 nm.
  • Step S22 forming a second protective layer on the sides of the first metal layer, the conductive layer and the second metal layer by a patterning process.
  • the electrodes are gate electrodes and/or source and drain electrodes.
  • a method for fabricating a thin film transistor includes: forming a conductive layer on a substrate and a first protective layer disposed on a surface of the conductive layer, and forming a second protective layer on a side of the conductive layer to form a protective layer and a conductive layer.
  • the electrode wherein the protective layer comprises: a first protective layer and a second protective layer, the second protective layer is used to isolate the conductive layer from the outside.
  • the second protective layer can be used to block oxygen and/or hydrogen.
  • a thin film transistor of a top gate structure, and a gate electrode and a source/drain electrode simultaneously including a conductive layer and a protective layer are taken as an example to further specifically describe a method of fabricating a thin film transistor provided by some embodiments of the present disclosure.
  • the patterning process includes: photoresist coating, exposure, development, etching, photoresist stripping and the like.
  • Step 201 forming an active layer 21 and a gate insulating layer 22 on the substrate 20, depositing a first metal thin film, a conductive thin film and a second metal thin film on the substrate 20 on which the active layer 21 and the gate insulating layer 22 are formed, by a patterning process
  • the first metal film, the conductive film, and the second metal film are processed to form the first metal layer 11, the conductive layer 10, and the second metal layer 12.
  • step 201 in this embodiment refers to steps 101-103 in some embodiments of the present disclosure, and details are not described herein again.
  • Step 202 depositing a protective material film 100 on the substrate 20 on which the first metal layer 11, the conductive layer 10 and the second metal layer 12 are formed, as shown in FIG. 7A.
  • the protective material film covers at least the second metal layer and sides of the first metal layer, the conductive layer, and the second metal layer.
  • the material of the protective material film 100 is aluminum nitride, and the thickness of the protective material film 100 is 5-50 nm.
  • Step 203 processing the protective material film 100 by a patterning process, forming a second protective layer 13 disposed on the sides of the first metal layer 11, the conductive layer 10, and the second metal layer 12 to form a gate electrode 23 including a conductive layer and a protective layer.
  • a portion of the protective material film on the sides of the first metal layer, the conductive layer, and the second metal layer may be retained by a patterning process to remove undesired portions of the protective material film, Thereby, the first metal layer 11, the conductive layer 10, and the second metal layer 12 are formed.
  • the protective layer includes a first metal layer 11 , a second metal layer 12 , and a second protective layer 13 .
  • Step 204 forming an interlayer insulating layer 24, a source/drain electrode 25, and a passivation layer 26 on the substrate 20, as shown in FIG.
  • the material of the interlayer insulating layer 24 and the passivation layer 26 is silicon oxide.
  • the source/drain electrodes 25 are formed by the processes of steps 201-203, and are not described herein again.
  • Some embodiments of the present disclosure provide an array substrate including the aforementioned device such as a thin film transistor.
  • the device in this embodiment can adopt the device provided according to the above embodiments.
  • the implementation principle and implementation effect are similar, and will not be described here.
  • some embodiments of the present disclosure provide a display device including an array substrate.
  • the display device includes a display panel, and the display panel includes an array substrate, and the array substrate is an array substrate provided by some embodiments.
  • the implementation principle and implementation effect are similar, and will not be described here.
  • the display device may be a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, or the like.
  • OLED organic light-emitting diode
  • a product or part that has a display function Embodiments of the present disclosure are not limited thereto.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明实施例公开了一种电极结构及其制作方法、薄膜晶体管和阵列基板。提供了一种电极结构，包括：包括保护层和导电层(10)的导电体(23或25)，所述保护层包括：设置在所述导电层表面的第一保护层(11和12)和设置在至少导电层侧面的第二保护层(13)，所述第二保护层用于将所述导电层与外部隔离。

Description

电极结构及其制作方法、薄膜晶体管和阵列基板
相关申请的交叉引用
本申请要求于2017年8月30日提交的中国申请No.201710769888.9以及于2017年8月30提交的中国申请No.201721104937.9的优先权，并通过引用将其全部内容并入在此。
技术领域
本公开实施例涉及显示技术领域，具体涉及一种电极结构及其制作方法、薄膜晶体管和阵列基板。
背景技术
随着薄膜晶体管(Thin Film Transistor，简称TFT)液晶显示技术的不断发展，具备功耗低、分辨率高、反应速度快以及开口率高等特点的TFT显示装置逐渐成为主流，已被广泛应用于各种电子设备，如液晶电视、智能手机、平板电脑以及数字电子设备中。薄膜晶体管TFT可以包括：有源层、栅绝缘层、栅电极、层间绝缘层、源漏电极和钝化层。
然而，薄膜晶体管在高温高湿的环境下，电极结构的表面易产生气泡甚至破裂进而影响其导电性，降低了薄膜晶体管的良品率。
发明内容
根据本公开一个方面，提供了一种电极结构，包括：包括保护层和导电层的导电体；所述保护层包括：设置在所述导电层表面的第一保护层和设置在至少导电层侧面的第二保护层，所述第二保护层用于将所述导电层与外部隔离。
在一个实施例中，所述第一保护层和所述第二保护层的材料不同。在一个实施例中，所述第二保护层可以用于阻隔氧和/或氢。
在一个实施例中，所述第一保护层包括：第一金属层和第二金属层，所述第一金属层设置在导电层靠近基底的一侧，所述第二金属层设置在导电层远离基底的一侧。
在一个实施例中，所述第二保护层设置为覆盖所述导电层的侧面，所述第二保护层的高度基本等于所述导电层的厚度。在一个实施例中，所述第二保护层设置为完全覆盖所述 导电层的侧面。
在一个实施例中，所述第二保护层设置为覆盖所述第一金属层、所述导电层和所述第二金属层的侧面，所述第二保护层的高度基本等于第一金属层、导电层和第二金属层的厚度之和。
在一个实施例中，导电层的材料包括铝，所述第二保护层的材料包括氮化铝。在一个实施例中，所述第一金属层和第二金属层的材料不同。
在一个实施例中，所述第二保护层的厚度为5-50纳米。
在一个实施例中，第一金属层和第二金属层的材料包括：钼(Mo)。
在一个实施例中，所述导电层包括金属材料。
根据本公开另一方面，提供了一种薄膜晶体管，其可以包括根据任一实施例所述的电极结构，所述导电体为所述薄膜晶体管的下列中的至少一个：栅电极、源电极、漏电极、或布线。
根据本公开另一个方面，提供了一种阵列基板，其包括如前面所述任一方面或实施例的薄膜晶体管。
根据本公开另一个方面，提供了一种电极结构的制作方法，包括：在基底上形成导电层和用于导电层的第一保护层；以及形成第二保护层，所述第二保护层至少覆盖所述导电层的侧面，所述第二保护层用于将所述导电层与外部隔离。
在一些实施例中，所述第一保护层和所述第二保护层的材料不同。在一些实施例中，所述第二保护层用于阻隔氧和/或氢。
在一个实施例中，所述在基底上形成导电层和设置在导电层表面的第一保护层包括：在基底上形成第一金属薄膜、导电薄膜和第二金属薄膜的叠层；对所述叠层进行构图处理，以形成第一金属层、所述导电层和第二金属层，其中，第一保护层包括：第一金属层和第二金属层。
在一个实施例中，形成第二保护层包括：采用氮气等离子对所述导电层进行处理，形成所述第二保护层。
在一个实施例中，形成第二保护层包括：在形成有第一金属层、导电层和第二金属层的基底上沉积保护材料薄膜，所述保护材料薄膜至少覆盖所述第二金属层以及所述第一金属层、导电层和第二金属层的侧面；通过构图工艺使得所述保护材料薄膜在第一金属层、 导电层和第二金属层的侧面上的部分保留，从而形成所述第二保护层。
在一个实施例中，所述导电体为薄膜晶体管的下列中的至少一个：栅电极、源电极、漏电极、或布线。
在一个实施例中，所述导电薄膜由金属材料形成。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为传统薄膜晶体管的简化结构示意图；
图2为本公开一些实施例提供的电极的结构示意图；
图3为本公开一些实施例提供的薄膜晶体管的结构示意图；
图4为本公开一些实施例提供的电极的结构示意图；
图5为本公开一些实施例提供的薄膜晶体管的结构示意图；
图6为本公开一些实施例提供的薄膜晶体管制作方法的流程图；
图6A为本公开一些实施例提供的薄膜晶体管制作方法的示意图；
图6B为本公开一些实施例提供的薄膜晶体管制作方法的示意图；
图6C为本公开一些实施例提供的薄膜晶体管制作方法的示意图；
图6D为本公开一些实施例提供的薄膜晶体管制作方法的示意图；
图7A为本公开一些实施例提供的薄膜晶体管制作方法的示意图；和
图7B为本公开一些实施例提供的薄膜晶体管制作方法的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
图1为传统薄膜晶体管的简化结构示意图。如图1所述，在基底1上形成电极，电极之上设置材料为氧化硅的绝缘层5。电极包括：材料为钼的第一层2、材料为铝的第二层3和材料为钼的第三层4。其中，电极为栅电极或源漏电极。当电极为栅电极时，在顶栅结构中该绝缘层可以为层间绝缘层，在底栅结构中该绝缘层可以为栅绝缘层。当电极为源漏电极时，绝缘层可以为钝化层。在实际制作过程中，在形成绝缘层5之前或形成过程中，第二层3的边缘部分会被氧化形成氧化铝。因此，形成绝缘层5之后，第二层3边缘的氧化铝会与氧化硅接触。
发明人发现，薄膜晶体管在制成之后，通常需要将其放置在高温高湿的环境下进行信赖性评价。一方面，在高温高湿的环境下，氧化硅中可能始终存在氢原子。另一方面，可能由多种制造工艺引入诸如水汽等含氢杂质。由于氧化铝的原子间隙比较大，氢原子会随性“游走”，打破金属铝和氧化铝之间的联系，使得一部分铝原子可自由运动，从而在金属铝的一侧形成很多坑。随着坑的不断长大，“游走”的氢原子具有足够的空间形成氢分子并对金属铝的表面产生压力。当坑的直径大到某一临界尺寸时，金属铝的表面就会被撑得发生塑性变形，并向外鼓出形成气泡。而气泡密度足够大时，形成气泡的金属铝的表面会破裂，导致第二层的接触电阻不均匀甚至第二层的金属断裂，严重影响了电极的导电性，降低了薄膜晶体管的良品率。此外，当气泡密度足够大时，电极上的氧化膜保护层便会脱落，最终导致失效。
图2为本公开一些实施例提供的电极的结构示意图；图3为本公开一些实施例提供的薄膜晶体管的结构示意图。如图2和3所示，薄膜晶体管包括：栅电极23和源电极/漏电极25。栅电极23和/或源电极/漏电极25为包括保护层和导电层10的电极。保护层包括：设置在导电层10表面的第一保护层(11和12)和设置在导电层10侧面的第二保护层13，第二保护层13用于将所述导电层与外部隔离。例如，如图中所示，第二保护层13可以将导电层与氧化硅阻隔开。
在本实施例中，薄膜晶体管还包括：设置在基底20上的有源层21、栅绝缘层22、层间绝缘层24和钝化层26，如图3所示。需要说明的是，薄膜晶体管的结构可以为顶栅结构，也可以为底栅结构。图3是以顶栅结构为例进行说明的。另外，图3还是以栅电极和源漏电极均为本公开实施例提供的电极为例进行说明的。这里还应理解，本公开的实施例的原理可以适用于多种多样的器件，包括但不限于半导体器件，诸如晶体管等的有源器件， 以及无源器件等。另外，尽管这里以电极作为导电体的示例进行说明，显然不公开不限于此。例如，在其他实施例中，可以适当地将本公开的实施例的原理应用诸如布线、焊盘等导电体。
具体的，第一保护层包括：第一金属层11和第二金属层12，第一金属层11设置在导电层10靠近基底20的下表面，第二金属层12设置在导电层10远离基底20的上表面。需要了解的是，在一些实施例中，如图中所示的，第一金属层11在基底20上的正投影大于或者等于导电层10在基底20上的正投影，导电层10在基底20上的正投影大于或者等于第二金属层12在基底20上的正投影。导电层10的形状可以为棱台或棱柱结构，或者还可以为圆台或圆柱结构。第一金属层11和第二金属层12的形状与导电层10的形状相同。本公开实施例不限于在此示出或说明的实施例。
其中，第二保护层13设置在导电层10的侧面，且第二保护层13的高度h等于导电层10的厚度。需要了解的是，在一些实施例中，第二保护层13靠近基底20的下表面的长度l 1的两倍与导电层10靠近基底10的下表面的长度l 2之和小于或等于第一金属层11远离基底20的上表面的长度。显然本公开不限于。在一些实施例中，所述第一保护层和所述第二保护层的材料不同。另外，在一些实施例中，所述第二保护层可以被设置为完全覆盖所述导电层的侧面。
可选地，第一金属层11和第二金属层12的材料包括钼。需要说明的是，第一金属层11和第二金属层12不仅可以导电，还可以用于保护导电层10，避免导电层被氧化。在一些实施例中，所述第一金属层和第二金属层的材料可以不同。
导电层10可以由金属材料形成。可选地，导电层10的材料包括：铝。
可选地，第二保护层13的材料包括：氮化铝。需要说明的是，第二保护层13还可以为其他的氢的渗透能力较弱的材料。本公开不限于在此示出或说明的实施例。
具体的，第二保护层13的形状与导电层10的形状有关。例如，若导电层10的形状为棱台或棱柱，则第二保护层13的横截面的形状为平行四边形。若导电层10的形状为圆台或圆柱，则第二保护层13的横截面的形状为矩形。本公开不限于在此示出或说明的实施例。
可选地，第二保护层13的厚度为大约5-50纳米。
本公开实施例提供的薄膜晶体管，可以包括：栅电极和源漏电极，栅电极和/或源漏 电极为包括保护层和导电层的电极，保护层包括：设置在导电层表面的第一保护层和设置在导电层侧面的第二保护层，第二保护层用于将所述导电层与外部隔离。第二保护层可以用于阻隔氧和/或氢。通过在电极的导电层的侧面设置第二保护层，既可以避免氢进入导电层或其界面，也可以避免由于导电层的氧化而形成金属/金属氧化物界面(例如，铝/氧化铝界面)从而避免氢进入这样的界面。如此，避免了由于氢导致的电极的接触电阻不均匀甚至断裂，以及保护膜的破裂等，进而改善了器件中电极等导电体的导电性，提高了器件的良品率和可靠性。
图4为本公开一些实施例提供的电极的结构示意图；图5为本公开一些实施例提供的薄膜晶体管的结构示意图。如图4和5所示，薄膜晶体管包括：栅电极23和源/漏电极25。栅电极23和/或源漏电极25为包括保护层和导电层10的电极，包括：设置在导电层10表面的第一保护层和设置在导电层10侧面的第二保护层13，第二保护层13用于将所述导电层与外部(例如，外部的氧化硅等)隔离。在一些实施例中，所述第一保护层和所述第二保护层的材料不同。在一些实施例中，所述第二保护层用于阻隔氧和/或氢。
在本实施例中，薄膜晶体管还包括：设置在基底20上的有源层21、栅绝缘层22、层间绝缘层24和钝化层26。需要说明的是，薄膜晶体管的结构可以为顶栅结构，也可以为底栅结构。图5是以顶栅结构为例进行说明的，另外，图5还是以栅电极和源漏电极均为本公开实施例提供的电极为例进行说明的。
具体的，第一保护层包括：第一金属层11和第二金属层12，第一金属层11设置在导电层10靠近基底20的下表面，第二金属层12设置在导电层10远离基底20的上表面。需要了解的是，第一金属层11在基底20上的正投影大于或者等于导电层10在基底20上的正投影，导电层10在基底20上的正投影大于或者等于第二金属层12在基底20上的正投影。导电层10的形状可以为棱台或棱柱结构，或者还可以为圆台或圆柱结构。第一金属层11和第二金属层12的形状为导电层10的形状相同，本公开实施例不限于在此示出或说明的实施例。
其中，第二保护层13设置在第一金属层11、导电层10和第二金属层12的侧面。第二保护层13的高度h等于第一金属层11、导电层10和第二金属层12的厚度之和。
可选地，第一金属层11和第二金属层12的材料包括但不限于钼。需要说明的是，第一金属层11和第二金属层12不仅可以导电，还可以用于保护导电层10，避免导电层被氧 化。
导电层10可以由金属材料形成。可选地，导电层10的材料包括：铝。
可选地，第二保护层13的材料包括：氮化铝。需要说明的是，第二保护层13还可以为其他的氢的渗透能力较弱的材料，本公开不限于在此示出或说明的实施例。
具体的，第二保护层13的形状与导电层的形状有关。例如，若导电层的形状为棱台或棱柱，则第二保护层13的横截面的形状为平行四边形。若导电层的形状为圆台或圆柱，则第二保护层13的横截面的形状为矩形。本公开不限于在此示出或说明的实施例。
可选地，第二保护层13的厚度为大约5-50纳米。
本公开实施例提供的薄膜晶体管，包括：栅电极和源漏电极，栅电极和/或源漏电极为包括保护层和导电层的电极，保护层包括：设置在导电层表面的第一保护层和设置在导电层侧面的第二保护层。第二保护层用于阻隔氧和/或氢。通过在电极的导电层的侧面设置第二保护层，可以避免了由于氢“游走”并进入导电层而导致的电极的接触电阻不均匀甚至断裂，以及保护膜的破裂等，进而改善了器件中电极等导电体的导电性，提高了器件的良品率和可靠性。
本公开一些实施例提供了一种薄膜晶体管制作方法。图6为本公开一些实施例提供的薄膜晶体管制作方法的流程图。如图6所示，该制作方法具体包括以下步骤：
步骤S1、在基底上形成导电层和设置在导电层表面的第一保护层。
具体的，步骤S1具体包括：
步骤S11、在基底上依次形成(例如，沉积)第一金属薄膜、导电薄膜和第二金属薄膜的叠层。
具体的，可以采用化学气相沉积(chemical vapor deposition，简称CVD)工艺、蒸镀工艺或溅射工艺等方法沉积第一金属薄膜、导电薄膜和第二金属薄膜。
可选地，第一金属薄膜和第二金属薄膜的材料均为例如钼。导电薄膜可以由金属材料形成，例如铝。
步骤S12、通过构图工艺形成第一金属层、导电层和第二金属层。换而言之，可以对所述叠层进行构图，以与所述叠层中的薄膜对应地形成第一金属层、导电层和第二金属层。
其中，构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等工艺。第一保护层包括：第一金属层和第二金属层。
需要了解的是，第一金属层在基底上的正投影大于或者等于导电层在基底上的正投影，导电层在基底上的正投影大于或者等于第二金属层在基底上的正投影。导电层的形状可以为棱台或棱柱结构，或者还可以为圆台或圆柱结构。第一金属层和第二金属层的形状为导电层的形状相同。本公开实施例不限于在此示出或说明的实施例。
步骤S2、在导电层的侧面形成第二保护层，以形成包括保护层和导电层的电极。
其中，保护层包括：第一保护层和第二保护层，第二保护层用于将所述导电层与外部隔离，例如阻隔导电层与氧化硅接触。
具体的，步骤S2具体包括：采用氮气等离子对导电层进行处理，形成设置在导电层的侧面的第二保护层。
在一些实施例中，第二保护层的材料为氮化铝。第二保护层的厚度可以为5-50纳米。需要说明的是，第二保护层的厚度可以通过氮气的含量来控制。本公开不限于在此示出或说明的实施例。
在本实施例中，通过采用氮气等离子处理简化了工艺，避免使用掩膜板，降低了制作工艺的复杂度，简化了薄膜晶体管的制作工艺。
在本实施例中，电极可以为栅电极和/或源漏电极。
本公开实施例提供的薄膜晶体管制作方法，包括：在基底上形成导电层和设置在导电层表面的第一保护层，在导电层的侧面形成第二保护层，以形成包括保护层和导电层的电极，其中，保护层包括：第一保护层和第二保护层，第二保护层用于将所述导电层与外部隔离。所述第二保护层可以用于阻隔氧和/或氢。通过在电极的导电层的侧面设置第二保护层，可以避免了由于氢“游走”并进入导电层而导致的电极的接触电阻不均匀甚至断裂，以及保护膜的破裂等，进而改善了器件中电极等导电体的导电性，提高了器件的良品率和可靠性。
下面结合图6A-6D，以顶栅结构的薄膜晶体管，且栅电极和源漏电极同时包括导电层和保护层为例，进一步地具体描述本公开一些实施例提供的薄膜晶体管制作方法。其中，构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工艺。
步骤101、在基底20上形成有源层21和栅绝缘层22，具体如图6A所示。
具体的，基底20的材料可以为例如玻璃或塑料。本公开实施例对于基底没有不作任何特别限定，本领域技术人员可以根据实际的需要也选择基底。进一步地，在形成有源层 21之前，可对基底20进行预清洗操作。
在一具体的实现方式中，有源层21的材料为多晶硅。本公开不限于此。有源层21可以由任何适当的半导体材料形成，例如但不限于，诸如硅、诸如IGZO等氧化物半导体等。
可选地，栅绝缘层22的材料可以为氧化硅和/或氮化硅。
步骤102、在形成有源层21和栅绝缘层22的基底20上沉积第一金属薄膜110、导电薄膜120和第二金属薄膜130，具体如图6B所示。
具体的，采用CVD工艺、蒸镀工艺或溅射工艺等方法沉积第一金属薄膜110、导电薄膜120和第二金属薄膜130。
其中，第一金属薄膜110和第二金属薄膜130的材料为钼，导电薄膜120的材料为铝。
步骤103、通过构图工艺处理第一金属薄膜110、导电薄膜120和第二金属薄膜130，形成第一金属层11、导电层10和第二金属层12，具体如图6C所示。
其中，第一保护层包括：第一金属层11和第二金属层12。
步骤104、采用氮气等离子对导电层10进行处理，形成设置在导电层10的侧面的第二保护层13，形成包括保护层和导电层的栅电极23，具体如图6D所示。
其中，保护层包括：第一金属层11、第二金属层12和第二保护层13。
步骤105、在基底20上形成层间绝缘层24、源漏电极25和钝化层26，具体如图3所示。
其中，层间绝缘层24和钝化层26的材料均为氧化硅。
具体的，源漏电极25采用步骤102-104的工艺制成，在此不再赘述。
本公开一些实施例提供了一种薄膜晶体管制作方法，该制作方法具体包括以下步骤：
步骤S1、在基底上形成导电层和设置在导电层表面的第一保护层。
具体的，步骤S1具体包括：
步骤S11、在基底上依次沉积第一金属薄膜、导电薄膜和第二金属薄膜。
具体的，采用化学气相沉积(chemical vapor deposition，简称CVD)工艺、蒸镀工艺或溅射工艺等方法沉积第一金属薄膜、导电薄膜和第二金属薄膜。
可选地，第一金属薄膜和第二金属薄膜的材料均为钼，导电薄膜的材料为铝。
步骤S12、通过构图工艺形成第一金属层、导电层和第二金属层。
其中，构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离等工艺。第一保 护层包括：第一金属层和第二金属层。
需要了解的是，第一金属层在基底上的正投影大于或者等于导电层在基底上的正投影，导电层在基底上的正投影大于或者等于第二金属层在基底上的正投影。导电层的形状可以为棱台或棱柱结构，或者还可以为圆台或圆柱结构。第一金属层和第二金属层的形状为导电层的形状相同。本公开实施例不限于在此示出或说明的实施例。
步骤S2、在导电层的侧面形成第二保护层，以形成包括保护层和导电层的电极。
其中，保护层包括：第一保护层和第二保护层，第二保护层用于将所述导电层与外部隔离。
具体的，步骤S2具体包括：
步骤S21、在形成有第一金属层、导电层和第二金属层的基底上沉积保护材料薄膜。
具体的，采用化学气相沉积(chemical vapor deposition，简称CVD)工艺、蒸镀工艺或溅射工艺等方法沉积保护材料薄膜。
其中，保护材料薄膜的材料可以为氮化铝。保护材料薄膜的厚度可以为5-50纳米。
步骤S22、通过构图工艺在第一金属层、导电层和第二金属层的侧面形成第二保护层。
在本实施例中，电极为栅电极和/或源漏电极。
本公开实施例提供的薄膜晶体管制作方法，包括：在基底上形成导电层和设置在导电层表面的第一保护层，在导电层的侧面形成第二保护层，以形成包括保护层和导电层的电极，其中，保护层包括：第一保护层和第二保护层，第二保护层用于将所述导电层与外部隔离。所述第二保护层可以用于阻隔氧和/或氢。通过在电极的导电层的侧面设置阻隔氧的第二保护层，可以避免了由于氢“游走”并进入导电层而导致的电极的接触电阻不均匀甚至断裂，以及保护膜的破裂等，进而改善了器件中电极等导电体的导电性，提高了器件的良品率和可靠性。
下面结合图7A-7B，以顶栅结构的薄膜晶体管，且栅电极和源漏电极同时包括导电层和保护层为例，进一步地具体描述本公开一些实施例提供的薄膜晶体管制作方法。其中，构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工艺。
步骤201、在基底20上形成有源层21和栅绝缘层22，在形成有源层21和栅绝缘层22的基底20上沉积第一金属薄膜、导电薄膜和第二金属薄膜，通过构图工艺处理第一金属薄膜、导电薄膜和第二金属薄膜，形成第一金属层11、导电层10和第二金属层12。
具体的，本实施例中的步骤201具体参考本公开一些实施例中的步骤101-103，在此不再赘述。
步骤202、在形成有第一金属层11、导电层10和第二金属层12的基底20上沉积保护材料薄膜100，具体如图7A所示。所述保护材料薄膜至少覆盖所述第二金属层以及所述第一金属层、导电层和第二金属层的侧面。
其中，保护材料薄膜100的材料为氮化铝，保护材料薄膜100的厚度为5-50纳米。
步骤203、通过构图工艺处理保护材料薄膜100，形成设置在第一金属层11、导电层10和第二金属层12侧面的第二保护层13，以形成包括导电层和保护层的栅电极23，具体如图7B所示。在一个实施例中，可以通过构图工艺使得所述保护材料薄膜在第一金属层、导电层和第二金属层的侧面上的部分保留，而将所述保护材料薄膜的不期望的部分去除，从而形成所述第一金属层11、导电层10和第二金属层12。
其中，保护层包括：第一金属层11、第二金属层12和第二保护层13。
步骤204、在基底20上形成层间绝缘层24、源漏电极25和钝化层26，具体如图5所示。
其中，层间绝缘层24和钝化层26的材料均为氧化硅。
具体的，源漏电极25采用步骤201-203的工艺制成，在此不再赘述。
应理解，本公开的实施例的原理可以适用于多种多样的器件，包括但不限于：诸如晶体管等的有源器件，以及诸如接合线(bonding line)或布线(wiring)等的无源器件。另外，尽管这里以电极作为导电体的示例进行说明，显然不公开不限于此。例如，在其他实施例中，可以适当地将本公开的实施例的原理应用诸如布线、焊盘等导电体。
本公开一些实施例提供一种阵列基板，包括前述的诸如薄膜晶体管的器件。
其中，本实施例中的器件可以采用根据上述的实施例提供的器件。其实现原理和实现效果类似，在此不再赘述。
基于同样的发明构思，本公开一些实施例提供一种显示装置，包括阵列基板。
其中，显示装置包括显示面板，显示面板中包括阵列基板，阵列基板为采用一些实施例提供的阵列基板。其实现原理和实现效果类似，在此不再赘述。
具体的，显示装置可以为液晶显示面板、有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、 数码相框、导航仪等任何具有显示功能的产品或部件。本公开实施例不限于此。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。
本申请要求于2017年8月30日提交的中国申请No.201710769888.9以及于2017年8月30提交的中国申请No.201721104937.9的优先权，并通过引用将其全部内容并入在此。

Claims (20)

  1. 一种电极结构，包括：
    包括保护层和导电层；
    其中，所述保护层包括设置在所述导电层表面的第一保护层和设置在所述导电层侧面的第二保护层，所述第二保护层用于将所述导电层与外部隔离。
  2. 根据权利要求1所述的电极结构，其中，
    所述第一保护层和所述第二保护层的材料不同，
    所述第二保护层用于阻隔氧和/或氢。
  3. 根据权利要求1所述的电极结构，其中，所述第一保护层包括：第一金属层和第二金属层，所述第一金属层设置在导电层靠近基底的一侧，所述第二金属层设置在导电层远离基底的一侧。
  4. 根据权利要求3所述的电极结构，其中，所述第二保护层设置为覆盖所述导电层的侧面。
  5. 根据权利要求3所述的电极结构，其中，所述第二保护层设置为完全覆盖所述导电层的侧面。
  6. 根据权利要求3所述的电极结构，其中，所述第二保护层设置为覆盖所述第一金属层、所述导电层和所述第二金属层的侧面。
  7. 根据权利要求3所述的电极结构，其中，所述第一金属层和第二金属层的材料包括：钼。
  8. 根据权利要求3所述的电极结构，其中，所述第一金属层和第二金属层的材料不 同。
  9. 根据权利要求1-8任一所述的电极结构，其中，所述导电层的材料包括铝，所述第二保护层的材料包括氮化铝。
  10. 根据权利要求1所述的电极结构，其中，所述第二保护层的厚度为5-50纳米。
  11. 根据权利要求1所述的电极结构，其中所述导电层包括金属材料。
  12. 一种薄膜晶体管，包括如权利要求1-11中任一项所述的电极结构，其中所述导电体为所述薄膜晶体管的下列中的至少一个：栅电极、源电极、漏电极、或导线。
  13. 一种阵列基板，其中，包括如权利要求12所述的薄膜晶体管。
  14. 一种电极结构的制作方法，包括：
    在基底上形成导电层和用于导电层的第一保护层；以及
    形成第二保护层，所述第二保护层至少覆盖所述导电层的侧面，所述第二保护层用于将所述导电层与外部隔离。
  15. 根据权利要求14所述的方法，其中，
    所述第一保护层和所述第二保护层的材料不同，
    所述第二保护层用于阻隔氧和/或氢。
  16. 根据权利要求14所述的方法，其中，所述在基底上形成导电层和设置在导电层表面的第一保护层包括：
    在基底上形成第一金属薄膜、导电薄膜和第二金属薄膜的叠层；以及
    对所述叠层进行构图处理，以形成第一金属层、所述导电层和第二金属层，
    其中，所述第一保护层包括所述第一金属层和第二金属层。
  17. 根据权利要求16所述的方法，其中，形成第二保护层包括：
    采用氮气等离子对所述导电层进行处理，形成所述第二保护层。
  18. 根据权利要求16所述的方法，其中，形成第二保护层包括：
    在形成有第一金属层、导电层和第二金属层的基底上沉积保护材料薄膜，所述保护材料薄膜至少覆盖所述第二金属层以及所述第一金属层、导电层和第二金属层的侧面；以及
    通过构图工艺使得所述保护材料薄膜在第一金属层、导电层和第二金属层的侧面上的部分保留，从而形成所述第二保护层。
  19. 根据权利要求14所述的方法，其中，所述导电体为薄膜晶体管的下列中的至少一个：栅电极、源电极、漏电极、或布线。
  20. 根据权利要求16所述的方法，其中，其中所述导电薄膜由金属材料形成。
PCT/CN2018/089632 2017-08-30 2018-06-01 电极结构及其制作方法、薄膜晶体管和阵列基板 WO2019041934A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/326,256 US20200403102A1 (en) 2017-08-30 2018-06-01 Electrode structure and manufacturing method thereof, thin film transistor, and array substrate

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201721104937.9U CN207068871U (zh) 2017-08-30 2017-08-30 一种薄膜晶体管、阵列基板和显示装置
CN201721104937.9 2017-08-30
CN201710769888.9 2017-08-30
CN201710769888.9A CN107507868A (zh) 2017-08-30 2017-08-30 一种薄膜晶体管及其制作方法、阵列基板和显示装置

Publications (1)

Publication Number Publication Date
WO2019041934A1 true WO2019041934A1 (zh) 2019-03-07

Family

ID=65526156

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/089632 WO2019041934A1 (zh) 2017-08-30 2018-06-01 电极结构及其制作方法、薄膜晶体管和阵列基板

Country Status (2)

Country Link
US (1) US20200403102A1 (zh)
WO (1) WO2019041934A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114566507A (zh) * 2022-02-24 2022-05-31 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102668097A (zh) * 2009-11-13 2012-09-12 株式会社半导体能源研究所 半导体器件及其制造方法
CN104045066A (zh) * 2013-03-14 2014-09-17 王永年 一种制造氮化铝的方法
JP2016047961A (ja) * 2014-08-07 2016-04-07 イーメックス株式会社 窒化アルミニウム薄膜、窒化アルミニウム薄膜の形成方法、及び、電極材料
CN107507868A (zh) * 2017-08-30 2017-12-22 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN207068871U (zh) * 2017-08-30 2018-03-02 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102668097A (zh) * 2009-11-13 2012-09-12 株式会社半导体能源研究所 半导体器件及其制造方法
CN104045066A (zh) * 2013-03-14 2014-09-17 王永年 一种制造氮化铝的方法
JP2016047961A (ja) * 2014-08-07 2016-04-07 イーメックス株式会社 窒化アルミニウム薄膜、窒化アルミニウム薄膜の形成方法、及び、電極材料
CN107507868A (zh) * 2017-08-30 2017-12-22 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN207068871U (zh) * 2017-08-30 2018-03-02 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板和显示装置

Also Published As

Publication number Publication date
US20200403102A1 (en) 2020-12-24

Similar Documents

Publication Publication Date Title
US9601519B2 (en) Thin film transistor and display panel including the same
CN103745978B (zh) 显示装置、阵列基板及其制作方法
KR101346874B1 (ko) 반도체 장치 및 그 제조 방법
WO2013131380A1 (zh) 阵列基板及其制作方法和显示装置
US10340392B2 (en) Semiconductor device including mark portion and production method for same
WO2013170605A1 (zh) 薄膜晶体管阵列基板及其制造方法、显示面板、显示装置
WO2016000342A1 (zh) 阵列基板及其制作方法、显示装置
WO2015043220A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
WO2015100894A1 (zh) 显示装置、阵列基板及其制造方法
TWI497689B (zh) 半導體元件及其製造方法
WO2017202057A1 (zh) 电子器件、薄膜晶体管、以及阵列基板及其制作方法
TWI555183B (zh) 薄膜電晶體以及畫素結構
WO2019148579A1 (zh) 薄膜晶体管阵列基板及其制造方法
WO2016045238A1 (zh) 阵列基板及其制作方法、液晶显示装置
US20150311345A1 (en) Thin film transistor and method of fabricating the same, display substrate and display device
WO2015096307A1 (zh) 氧化物薄膜晶体管、显示器件、及阵列基板的制造方法
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
US10529750B2 (en) LTPS array substrate and method for producing the same
WO2015043078A1 (zh) 阵列基板及其制作方法和显示装置
WO2015010404A1 (zh) 薄膜晶体管及其制作方法、阵列基板及显示装置
CN103745954A (zh) 显示装置、阵列基板及其制造方法
US7923312B2 (en) Fabricating method of thin film transistor
WO2019210776A1 (zh) 阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法
WO2014046068A1 (ja) アクティブマトリックス基板、表示装置、及び、その製造方法
WO2019051864A1 (zh) 主动阵列开关的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18849953

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 14/09/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18849953

Country of ref document: EP

Kind code of ref document: A1