JP4278982B2 - 基板上に超小型電子ばね構造体を作製するための方法 - Google Patents
基板上に超小型電子ばね構造体を作製するための方法 Download PDFInfo
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Description
本発明は電気装置用の電気接点素子に関し、特に、輪郭を改善した、リソグラフィと同程度の超小型電子ばね接点に関する。
ハンドロス(Khandros)らに付与された米国特許第5,917,707号に記載されているような近年の技術的進歩により、半導体チップなどの基板にじかに実装できる小型で柔軟性が高く弾力のある超小型電子ばね接点が得られるようになっている。上記の’707特許には、基板に極細のワイヤをボンディングした上でワイヤに電気めっきをほどこして弾力のある素子を得るワイヤボンディング工程を利用して作られる超小型電子ばね接点が開示されている。これらの超小型電子接点は後工程などの用途において非常に都合のよいものであり、特にプローブカードの接点構造体として使う場合に、細いタングステンワイヤの代わりに超小型電子接点を用いることができ好都合であった。また、エルドリッジ(Eldridge)らに付与された米国特許第6,032,446号および同第5,983,493号などに記載されているように、このような基板実装型の超小型電子ばね接点は、半導体デバイス全般の電気的な接続を得る上で、特にウエハレベルの試験やバーンイン工程を実施する目的で非常に有利なものとなり得ることが知られている。特にファインピッチのばね接点は、ほとんどすべてのタイプの電子デバイスで一時的な電気接続と永久的な電気接続の両方を得ることをはじめとして信頼性の高い電子コネクタのアレイが必要なあらゆる用途に役立つことが見込まれるものである。
本発明によれば、超小型電子ばね構造体の作製方法ならびに、上記の需要に対処すると同時に段のある複数のリソグラフィ層を使わずに適切なz−延在部を達成するための方法が得られる。
本発明は、過去の作製方法の限界を克服する、超小型電子ばね構造体の作製方法に対する需要を満たすものである。以下の詳細な説明では、1枚またはそれ以上の図に示す同様の要素に同様の参照符号を用いるものとする。
Claims (38)
- 透過部分と不透明部分とを備えるスタンピングツールを使用して、基板上に成形面を形成する方法であって、
前記基板上の成形可能材料の層に、前記スタンピングツールを押圧する工程と、
前記スタンピングツールを通じて硬化刺激を与える工程であって、前記成形可能材料は、前記透過部分に対応する部分が硬化され、前記不透明部分に対応する部分が硬化されない、工程と、
前記成形可能材料の未硬化部分を除去する工程と、
を備える、方法。 - 前記押圧工程および前記付与工程を繰り返し行い、複数の硬化された成形面を形成する工程をさらに備える、請求項1に記載の方法。
- 前記成形面上の少なくとも一部に接触構造体を形成する工程をさらに備える、請求項2に記載の方法。
- 前記スタンピングツールが歯を備え、この歯が前記不透明部分と前記透過部分とを有し、
前記不透明部分が、前記成形可能材料内に形成される、前記基板表面への開口に対応し、
前記透過部分が前記成形面に対応する、
請求項1に記載の方法。 - 前記スタンピングツールはさらに、
各々が透過部分と不透明部分とを有する複数の歯と、
互いに隣接する前記歯同士を分離する、さらに別の不透明部分と、
を備える、請求項4に記載の方法。 - 前記硬化刺激が紫外線である、請求項1に記載の方法。
- 前記成形可能材料の硬化部分の少なくとも一部に、接触構造体を形成する工程をさらに備える、請求項1に記載の方法。
- 複数の導電性接触部材を備える電子部品上に、複数の導電性接触構造体を形成する方法であって、各接触構造体は、各接触部材に接続される土台と、梁とをそれぞれ備え、
前記電子部品上に、成形可能材料の層を成膜する工程と、
複数の突出領域と、複数の凹凸領域と、複数のくぼみ領域とを備えるスタンピングツールを提供する工程であって、各前記突出領域は、各前記接触構造体の土台を画定するとともに、前記電子部品上の各前記接触部材と対応し、各前記凹凸領域は、各前記接触構造体の梁を画定し、各前記くぼみ領域は、互いに隣接する前記接触構造体間の分離を画定する、工程と、
前記スタンピングツールの突出領域を、前記電子部品の前記接触部材に位置合わせする工程と、
前記成形可能材料に前記スタンピングツールを押圧する工程であって、前記複数の突出領域が、前記接触構造体の土台の前記成形可能材料内に、モールドを形成し、また、前記複数の凹凸領域が、前記接触構造体の梁の前記成形可能材料内に、梁用のモールドを形成する、工程と、
前記梁モールドおよび前記土台モールド内へ、接触構造体材料を堆積させる工程と、
を備える、方法。 - 前記電子部品上に成形可能材料の層を成膜する工程が、
モールド内に前記電子部品を置く工程と、
前記モールド内へ前記成形可能材料を射出する工程と、
をさらに備える、請求項8に記載の方法。 - 前記電子部品上に成膜した前記成形可能材料の層を平坦化する工程をさらに備える、請求項8に記載の方法。
- 前記成形可能材料に前記スタンピングツールを押圧する工程の間、前記スタンピングツールを加熱する工程をさらに備える、請求項8に記載の方法。
- 前記スタピングツールを加熱後、前記成形可能材料に押圧しながら前記スタンピングツールを冷却する工程をさらに備える、請求項11に記載の方法。
- 前記成形可能材料に押圧しながら前記スタンピングツールを冷却する工程をさらに備える、請求項8に記載の方法。
- 少なくとも一つの前記凹凸領域がリブ付きの表面を備える、請求項8に記載の方法。
- 少なくとも一つの前記凹凸領域が波形表面を備える、請求項8に記載の方法。
- 少なくとも一つの前記凹凸領域がV字形、U字形、または二股形からなる群から選択される、請求項8に記載の方法。
- 前記成形可能材料に前記スタンピングツールを押圧後、前記スタンピングツールを除去するとともに、前記成形可能材料上に、導電性の材料のシード層を成膜する工程と、
前記シード層上でマスキング材料の層をパターニングする工程であって、前記マスキング材料内のパターンは、前記梁モールドと土台モールドとの対に対応する、工程と、
を備え、
前記マスキング材料内のパターンを介して前記シード層上に前記接触材料を堆積することにより、前記モールド内へ前記接触材料を成膜する、
請求項8に記載の方法。 - 前記マスキング材料および前記成形可能材料を除去する工程を備える、請求項17に記載の方法。
- 前記スタンピングツールはさらに、前記成形可能材料内に複数のリップを形成するために配された複数の再進入歯を備える、請求項8に記載の方法。
- 前記成形可能材料が弾性を有する、請求項19に記載の方法。
- 接触構造体材料を成膜する工程は、無電界成膜プロセスを使用して前記接触構造体材料を成膜する工程を備える、請求項8に記載の方法。
- 前記電子部品が、半導体ウェハを構成する、互いに切り離されていない複数のダイを備える、請求項8に記載の方法。
- 前記接触部材が前記ダイの端子である、請求項22に記載の方法。
- 前記成形可能材料が、ポリメチルメタクリレート、ポリカーボネート、ポリウレタン、ABSプラスチック、フォトレジスト、ノボラック樹脂、エポキシ、およびワックスからなる群から選択される、請求項8に記載の方法。
- 前記成形可能材料が、ポリメチルメタクリレート、フォトポリマー、ノボラック樹脂、およびエポキシからなる群から選択される、請求項8に記載の方法。
- 前記成形可能材料が熱可塑性材料である、請求項8に記載の方法。
- 少なくとも透過部分を有するスタンピングツールを使用して、基板上に成形面を形成する方法であって、
前記基板上の成形可能材料の層に前記スタンピングツールを押圧する工程と、
前記スタンピングツールの透過部分を通じて、硬化刺激を付与する工程であって、前記成形可能材料の少なくとも一部が硬化される、工程と、
前記成形可能材料の少なくとも一部に、複数の導電性接触構造体を形成する工程と、
を備える、方法。 - 前記押圧工程および前記付与工程を繰り返し行い、複数の硬化された成形面を形成する工程をさらに備える、請求項27に記載の方法。
- 前記スタンピングツールは、第一部分と第二部分とを有する歯を備え、
前記第一部分が、前記成形可能材料内に形成される、前記基板の表面への開口に対応し、
前記第二部分が成形面に対応する、
請求項27に記載の方法。 - 前記スタンピングツールがさらに、
各々が第一部分と第二部分とを有する複数の歯と、
互いに隣接する前記歯同士を分離する、さらに別の第一部分と、
を備える、請求項29に記載の方法。 - 前記硬化刺激が紫外線である、請求項27に記載の方法。
- 前記基板が、複数の導電性接触部材を備える電子部品である、請求項27に記載の方法。
- モールド内に前記電子部品を置く工程と、
前記成形可能材料を前記モールド内へ射出する工程と、
をさらに備える、請求項32に記載の方法。 - 少なくとも一つの前記第二部分が、リブ付き表面を備える、請求項30に記載の方法。
- 少なくとも一つの前記第二部分が、波形表面を備える、請求項30に記載の方法。
- 少なくとも一つの前記第二部分が、V字形、U字形、または二股形からなる群から選択される、請求項30に記載の方法。
- 前記成形可能材料に前記スタンピングツールを押圧後、前記スタンピングツールを除去するとともに、前記成形可能材料上に、導電性の材料のシード層を成膜する工程と、
前記シード層上でマスキング材料の層をパターニングする工程であって、前記マスキング材料のパターンは、前記複数の導電性接触構造体用のモールドに対応する、工程と、
を備え、
前記マスキング材料内のパターンを介して前記シード層上に前記接触材料を堆積することにより、前記モールド内へ前記接触材料を成膜する、
請求項8に記載の方法。 - 前記接触構造体を形成する工程は、無電界成膜プロセスを使用して接触構造体材料を成膜する工程を備える、請求項27に記載の方法。
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US09/781,833 US6939474B2 (en) | 1999-07-30 | 2001-02-12 | Method for forming microelectronic spring structures on a substrate |
PCT/US2002/003938 WO2002064496A2 (en) | 2001-02-12 | 2002-02-06 | Method for forming microelectronic spring structures on a substrate |
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- 2002-02-06 JP JP2002564434A patent/JP4278982B2/ja not_active Expired - Fee Related
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- 2002-02-06 CN CNB028048245A patent/CN1272234C/zh not_active Expired - Fee Related
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101746975B1 (ko) | 2015-12-16 | 2017-06-13 | 최재규 | 포고핀의 제조 방법 및 그 방법에 의해 제조된 포고핀 |
Also Published As
Publication number | Publication date |
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KR101005246B1 (ko) | 2011-01-04 |
US20060019027A1 (en) | 2006-01-26 |
KR20090005230A (ko) | 2009-01-12 |
CN1527793A (zh) | 2004-09-08 |
TW512129B (en) | 2002-12-01 |
US20010044225A1 (en) | 2001-11-22 |
EP1777194A2 (en) | 2007-04-25 |
DE60220022T2 (de) | 2008-01-10 |
WO2002064496A3 (en) | 2003-08-14 |
KR100880104B1 (ko) | 2009-01-21 |
CN101024480A (zh) | 2007-08-29 |
US6939474B2 (en) | 2005-09-06 |
CN100579891C (zh) | 2010-01-13 |
EP1362005A2 (en) | 2003-11-19 |
AU2002243937A1 (en) | 2002-08-28 |
CN1272234C (zh) | 2006-08-30 |
KR20040026135A (ko) | 2004-03-27 |
WO2002064496A2 (en) | 2002-08-22 |
EP1362005B1 (en) | 2007-05-09 |
EP1777194A3 (en) | 2010-05-05 |
JP2004528996A (ja) | 2004-09-24 |
DE60220022D1 (de) | 2007-06-21 |
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