JP4262141B2 - 積層型チップバリスタ及びその製造方法 - Google Patents

積層型チップバリスタ及びその製造方法 Download PDF

Info

Publication number
JP4262141B2
JP4262141B2 JP2004173050A JP2004173050A JP4262141B2 JP 4262141 B2 JP4262141 B2 JP 4262141B2 JP 2004173050 A JP2004173050 A JP 2004173050A JP 2004173050 A JP2004173050 A JP 2004173050A JP 4262141 B2 JP4262141 B2 JP 4262141B2
Authority
JP
Japan
Prior art keywords
varistor
pair
internal electrodes
outer layer
mol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2004173050A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005353844A (ja
Inventor
大 松岡
克成 森合
毅彦 阿部
浩一 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP2004173050A priority Critical patent/JP4262141B2/ja
Priority to US11/137,584 priority patent/US7167352B2/en
Priority to KR1020050045463A priority patent/KR100674385B1/ko
Priority to DE102005026731.9A priority patent/DE102005026731B4/de
Priority to TW094119093A priority patent/TWI297504B/zh
Priority to CNB2005100767457A priority patent/CN100472673C/zh
Publication of JP2005353844A publication Critical patent/JP2005353844A/ja
Application granted granted Critical
Publication of JP4262141B2 publication Critical patent/JP4262141B2/ja
Anticipated expiration legal-status Critical
Active legal-status Critical Current

Links

Images

Landscapes

  • Thermistors And Varistors (AREA)
JP2004173050A 2004-06-10 2004-06-10 積層型チップバリスタ及びその製造方法 Active JP4262141B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2004173050A JP4262141B2 (ja) 2004-06-10 2004-06-10 積層型チップバリスタ及びその製造方法
US11/137,584 US7167352B2 (en) 2004-06-10 2005-05-26 Multilayer chip varistor
KR1020050045463A KR100674385B1 (ko) 2004-06-10 2005-05-30 적층형 칩 배리스터
DE102005026731.9A DE102005026731B4 (de) 2004-06-10 2005-06-09 Mehrschichtchipvaristor
TW094119093A TWI297504B (en) 2004-06-10 2005-06-09 Multilayer chip varistor
CNB2005100767457A CN100472673C (zh) 2004-06-10 2005-06-10 积层型片状变阻器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004173050A JP4262141B2 (ja) 2004-06-10 2004-06-10 積層型チップバリスタ及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008110349A Division JP4683068B2 (ja) 2008-04-21 2008-04-21 積層型チップバリスタ

Publications (2)

Publication Number Publication Date
JP2005353844A JP2005353844A (ja) 2005-12-22
JP4262141B2 true JP4262141B2 (ja) 2009-05-13

Family

ID=35581508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004173050A Active JP4262141B2 (ja) 2004-06-10 2004-06-10 積層型チップバリスタ及びその製造方法

Country Status (2)

Country Link
JP (1) JP4262141B2 (zh)
CN (1) CN100472673C (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2400605A1 (en) * 2009-04-23 2011-12-28 Panasonic Corporation Surge absorbing element
EP2381451B1 (en) * 2010-04-22 2018-08-01 Epcos AG Method for producing an electrical multi-layer component and electrical multi-layer component
CN102867822B (zh) * 2012-09-14 2014-11-19 深圳中科系统集成技术有限公司 一种esd保护器件及其制备方法
JP7285852B2 (ja) * 2018-03-05 2023-06-02 キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション エネルギー処理能力の改善されたカスケードバリスタ
DE102018116221B4 (de) * 2018-07-04 2022-03-10 Tdk Electronics Ag Vielschichtvaristor mit feldoptimiertem Mikrogefüge und Modul aufweisend den Vielschichtvaristor
JP7235492B2 (ja) * 2018-12-12 2023-03-08 Tdk株式会社 チップバリスタ
DE102020122299B3 (de) * 2020-08-26 2022-02-03 Tdk Electronics Ag Vielschichtvaristor und Verfahren zur Herstellung eines Vielschichtvaristors

Also Published As

Publication number Publication date
CN100472673C (zh) 2009-03-25
CN1707703A (zh) 2005-12-14
JP2005353844A (ja) 2005-12-22

Similar Documents

Publication Publication Date Title
KR100674385B1 (ko) 적층형 칩 배리스터
JP7262181B2 (ja) 積層セラミックコンデンサおよびその製造方法
KR101952843B1 (ko) 내부전극용 도전성 페이스트 조성물 및 이를 포함하는 적층 세라믹 전자부품
JP5163097B2 (ja) バリスタ
US9343522B2 (en) Ceramic powder, semiconductor ceramic capacitor, and method for manufacturing same
JP2005353845A (ja) 積層型チップバリスタ
JP4262141B2 (ja) 積層型チップバリスタ及びその製造方法
JP4571164B2 (ja) 電気的過大応力に対する保護のために使用されるセラミック材料、及びそれを使用する低キャパシタンス多層チップバリスタ
JP4683068B2 (ja) 積層型チップバリスタ
JP5696623B2 (ja) チップバリスタ
JP3064659B2 (ja) 積層型セラミック素子の製造方法
JP4710560B2 (ja) 積層型チップバリスタの製造方法
KR20130027784A (ko) 외부 전극용 도전성 페이스트, 이를 이용한 적층 세라믹 전자부품 및 이의 제조방법
JP2006344751A (ja) 積層型チップバリスタ及びその製造方法
JP4087359B2 (ja) 積層型チップバリスタ
JP4070780B2 (ja) 積層型チップバリスタ
KR20190019117A (ko) 내부전극용 도전성 페이스트 조성물 및 이를 포함하는 적층 세라믹 전자부품
JP4710654B2 (ja) 積層型チップバリスタの製造方法
JP4041082B2 (ja) バリスタ及びバリスタの製造方法
KR100834307B1 (ko) 적층형 칩 바리스터의 제조방법
JP5321570B2 (ja) チップバリスタ
JP5338795B2 (ja) チップバリスタ
JP2008270391A (ja) 積層型チップバリスタおよびその製造方法
JP5799672B2 (ja) チップバリスタ
JP2007080950A (ja) バリスタシート用ペーストの製造方法、積層型チップバリスタの製造方法、及び積層型チップバリスタ

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070629

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070710

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070910

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080219

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080421

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20080602

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090203

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090206

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120220

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4262141

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120220

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130220

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140220

Year of fee payment: 5