JP4209588B2 - 高速メモリ用自己タイミング回路及びその実現方法 - Google Patents

高速メモリ用自己タイミング回路及びその実現方法 Download PDF

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Publication number
JP4209588B2
JP4209588B2 JP2000518387A JP2000518387A JP4209588B2 JP 4209588 B2 JP4209588 B2 JP 4209588B2 JP 2000518387 A JP2000518387 A JP 2000518387A JP 2000518387 A JP2000518387 A JP 2000518387A JP 4209588 B2 JP4209588 B2 JP 4209588B2
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model
word line
core
memory
self
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Japanese (ja)
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JP2001521262A (ja
JP2001521262A5 (enExample
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コーナチャク・スティーブ・ピー．
ベッカー・スコット・ティー．
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ARM Inc
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ARM Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
JP2000518387A 1997-10-24 1998-10-20 高速メモリ用自己タイミング回路及びその実現方法 Expired - Lifetime JP4209588B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/956,981 1997-10-24
US08/956,981 US5999482A (en) 1997-10-24 1997-10-24 High speed memory self-timing circuitry and methods for implementing the same
PCT/US1998/021939 WO1999022376A1 (en) 1997-10-24 1998-10-20 High speed memory self-timing circuitry and methods for implementing the same

Publications (3)

Publication Number Publication Date
JP2001521262A JP2001521262A (ja) 2001-11-06
JP2001521262A5 JP2001521262A5 (enExample) 2006-01-05
JP4209588B2 true JP4209588B2 (ja) 2009-01-14

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Application Number Title Priority Date Filing Date
JP2000518387A Expired - Lifetime JP4209588B2 (ja) 1997-10-24 1998-10-20 高速メモリ用自己タイミング回路及びその実現方法

Country Status (6)

Country Link
US (1) US5999482A (enExample)
EP (1) EP1025565B1 (enExample)
JP (1) JP4209588B2 (enExample)
AU (1) AU1096899A (enExample)
DE (1) DE69815372T2 (enExample)
WO (1) WO1999022376A1 (enExample)

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* Cited by examiner, † Cited by third party
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US8201584B2 (en) 2007-11-28 2012-06-19 Ibiden Co., Ltd. Exhaust pipe

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JP4894095B2 (ja) * 2001-06-15 2012-03-07 富士通セミコンダクター株式会社 半導体記憶装置
JP4339532B2 (ja) * 2001-07-25 2009-10-07 富士通マイクロエレクトロニクス株式会社 セルフタイミング回路を有するスタティックメモリ
US6618309B2 (en) * 2001-10-09 2003-09-09 Analog Devices, Inc. Adjustable memory self-timing circuit
US6730842B2 (en) * 2001-12-19 2004-05-04 Lsi Logic Corporation Self-extraction panel hinge
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JP2005025896A (ja) 2003-07-04 2005-01-27 Sony Corp 半導体記憶装置、および半導体記憶装置の読み出し方法
US6947349B1 (en) 2003-09-03 2005-09-20 T-Ram, Inc. Apparatus and method for producing an output clock pulse and output clock generator using same
US7089439B1 (en) 2003-09-03 2006-08-08 T-Ram, Inc. Architecture and method for output clock generation on a high speed memory device
US7464282B1 (en) 2003-09-03 2008-12-09 T-Ram Semiconductor, Inc. Apparatus and method for producing dummy data and output clock generator using same
US6891774B1 (en) 2003-09-03 2005-05-10 T-Ram, Inc. Delay line and output clock generator using same
JP4050690B2 (ja) * 2003-11-21 2008-02-20 株式会社東芝 半導体集積回路装置
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US8116159B2 (en) * 2005-03-30 2012-02-14 Ovonyx, Inc. Using a bit specific reference level to read a resistive memory
US7668029B2 (en) 2006-08-11 2010-02-23 Freescale Semiconductor, Inc Memory having sense time of variable duration
US7518947B2 (en) * 2006-09-28 2009-04-14 Freescale Semiconductor, Inc. Self-timed memory having common timing control circuit and method therefor
US7522461B2 (en) * 2006-11-06 2009-04-21 Infineon Technologies Flash Gmbh & Co. Kg Memory device architecture and method for improved bitline pre-charge and wordline timing
DE102006054781A1 (de) * 2006-11-21 2008-05-29 Qimonda Flash Gmbh Speichereinrichtung-Architektur und Verfahren zum verbesserten Bitleitung-Vorladen und Wortleitung-Timing
US7746716B2 (en) * 2007-02-22 2010-06-29 Freescale Semiconductor, Inc. Memory having a dummy bitline for timing control
US8233337B2 (en) * 2009-10-19 2012-07-31 International Business Machines Corporation SRAM delay circuit that tracks bitcell characteristics
JP5539916B2 (ja) 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
US9384790B2 (en) 2012-07-30 2016-07-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory device with separately controlled sense amplifiers
US8848414B2 (en) 2012-10-22 2014-09-30 International Business Machines Corporation Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system
US8730750B1 (en) 2012-10-28 2014-05-20 Lsi Corporation Memory device with control circuitry for generating a reset signal in read and write modes of operation
JP5732575B2 (ja) * 2014-05-01 2015-06-10 ルネサスエレクトロニクス株式会社 半導体装置
EP3204060A1 (en) * 2014-10-07 2017-08-16 Yissum Research Development Company of the Hebrew University of Jerusalem Ltd. On-demand degradable medical devices
US9881687B2 (en) * 2015-12-18 2018-01-30 Texas Instruments Incorporated Self-latch sense timing in a one-time-programmable memory architecture
US10156842B2 (en) 2015-12-31 2018-12-18 General Electric Company Device enrollment in a cloud service using an authenticated application
US9905315B1 (en) * 2017-01-24 2018-02-27 Nxp B.V. Error-resilient memory device with row and/or column folding with redundant resources and repair method thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8201584B2 (en) 2007-11-28 2012-06-19 Ibiden Co., Ltd. Exhaust pipe

Also Published As

Publication number Publication date
AU1096899A (en) 1999-05-17
JP2001521262A (ja) 2001-11-06
WO1999022376A1 (en) 1999-05-06
US5999482A (en) 1999-12-07
EP1025565A4 (en) 2001-04-25
EP1025565B1 (en) 2003-06-04
EP1025565A1 (en) 2000-08-09
DE69815372D1 (de) 2003-07-10
DE69815372T2 (de) 2004-04-29

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