AU1096899A - High speed memory self-timing circuitry and methods for implementing the same - Google Patents

High speed memory self-timing circuitry and methods for implementing the same

Info

Publication number
AU1096899A
AU1096899A AU10968/99A AU1096899A AU1096899A AU 1096899 A AU1096899 A AU 1096899A AU 10968/99 A AU10968/99 A AU 10968/99A AU 1096899 A AU1096899 A AU 1096899A AU 1096899 A AU1096899 A AU 1096899A
Authority
AU
Australia
Prior art keywords
implementing
methods
high speed
same
speed memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU10968/99A
Other languages
English (en)
Inventor
Scott T. Becker
Steve P. Kornachuk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Physical IP Inc
Original Assignee
Artisan Components Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Artisan Components Inc filed Critical Artisan Components Inc
Publication of AU1096899A publication Critical patent/AU1096899A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
AU10968/99A 1997-10-24 1998-10-20 High speed memory self-timing circuitry and methods for implementing the same Abandoned AU1096899A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/956,981 US5999482A (en) 1997-10-24 1997-10-24 High speed memory self-timing circuitry and methods for implementing the same
US08956981 1997-10-24
PCT/US1998/021939 WO1999022376A1 (en) 1997-10-24 1998-10-20 High speed memory self-timing circuitry and methods for implementing the same

Publications (1)

Publication Number Publication Date
AU1096899A true AU1096899A (en) 1999-05-17

Family

ID=25498928

Family Applications (1)

Application Number Title Priority Date Filing Date
AU10968/99A Abandoned AU1096899A (en) 1997-10-24 1998-10-20 High speed memory self-timing circuitry and methods for implementing the same

Country Status (6)

Country Link
US (1) US5999482A (enExample)
EP (1) EP1025565B1 (enExample)
JP (1) JP4209588B2 (enExample)
AU (1) AU1096899A (enExample)
DE (1) DE69815372T2 (enExample)
WO (1) WO1999022376A1 (enExample)

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US6629223B2 (en) * 1998-10-06 2003-09-30 Texas Instruments Incorporated Method and apparatus for accessing a memory core multiple times in a single clock cycle
US6388931B1 (en) * 1999-02-25 2002-05-14 Micron Technology, Inc. Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
US6181626B1 (en) 2000-04-03 2001-01-30 Lsi Logic Corporation Self-timing circuit for semiconductor memory devices
US6212117B1 (en) * 2000-06-07 2001-04-03 Hitachi Ltd. Duplicate bitline self-time technique for reliable memory operation
US6222791B1 (en) * 2000-06-15 2001-04-24 Artisan Components, Inc. Slew tolerant clock input buffer and a self-timed memory core thereof
JP4894095B2 (ja) * 2001-06-15 2012-03-07 富士通セミコンダクター株式会社 半導体記憶装置
JP4339532B2 (ja) * 2001-07-25 2009-10-07 富士通マイクロエレクトロニクス株式会社 セルフタイミング回路を有するスタティックメモリ
US6618309B2 (en) * 2001-10-09 2003-09-09 Analog Devices, Inc. Adjustable memory self-timing circuit
US6730842B2 (en) * 2001-12-19 2004-05-04 Lsi Logic Corporation Self-extraction panel hinge
US6980481B1 (en) * 2001-12-20 2005-12-27 Lsi Logic Corporatiion Address transition detect control circuit for self timed asynchronous memories
JP2005025896A (ja) 2003-07-04 2005-01-27 Sony Corp 半導体記憶装置、および半導体記憶装置の読み出し方法
US6947349B1 (en) 2003-09-03 2005-09-20 T-Ram, Inc. Apparatus and method for producing an output clock pulse and output clock generator using same
US7089439B1 (en) 2003-09-03 2006-08-08 T-Ram, Inc. Architecture and method for output clock generation on a high speed memory device
US7464282B1 (en) 2003-09-03 2008-12-09 T-Ram Semiconductor, Inc. Apparatus and method for producing dummy data and output clock generator using same
US6891774B1 (en) 2003-09-03 2005-05-10 T-Ram, Inc. Delay line and output clock generator using same
JP4050690B2 (ja) * 2003-11-21 2008-02-20 株式会社東芝 半導体集積回路装置
WO2005052944A1 (ja) * 2003-11-28 2005-06-09 Fujitsu Limited セルフタイミング回路を有する半導体メモリ
US8116159B2 (en) * 2005-03-30 2012-02-14 Ovonyx, Inc. Using a bit specific reference level to read a resistive memory
US7668029B2 (en) 2006-08-11 2010-02-23 Freescale Semiconductor, Inc Memory having sense time of variable duration
US7518947B2 (en) * 2006-09-28 2009-04-14 Freescale Semiconductor, Inc. Self-timed memory having common timing control circuit and method therefor
US7522461B2 (en) * 2006-11-06 2009-04-21 Infineon Technologies Flash Gmbh & Co. Kg Memory device architecture and method for improved bitline pre-charge and wordline timing
DE102006054781A1 (de) * 2006-11-21 2008-05-29 Qimonda Flash Gmbh Speichereinrichtung-Architektur und Verfahren zum verbesserten Bitleitung-Vorladen und Wortleitung-Timing
US7746716B2 (en) * 2007-02-22 2010-06-29 Freescale Semiconductor, Inc. Memory having a dummy bitline for timing control
JP5000466B2 (ja) 2007-11-28 2012-08-15 イビデン株式会社 排気管
US8233337B2 (en) * 2009-10-19 2012-07-31 International Business Machines Corporation SRAM delay circuit that tracks bitcell characteristics
JP5539916B2 (ja) 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
US9384790B2 (en) 2012-07-30 2016-07-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory device with separately controlled sense amplifiers
US8848414B2 (en) 2012-10-22 2014-09-30 International Business Machines Corporation Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system
US8730750B1 (en) 2012-10-28 2014-05-20 Lsi Corporation Memory device with control circuitry for generating a reset signal in read and write modes of operation
JP5732575B2 (ja) * 2014-05-01 2015-06-10 ルネサスエレクトロニクス株式会社 半導体装置
EP3204060A1 (en) * 2014-10-07 2017-08-16 Yissum Research Development Company of the Hebrew University of Jerusalem Ltd. On-demand degradable medical devices
US9881687B2 (en) * 2015-12-18 2018-01-30 Texas Instruments Incorporated Self-latch sense timing in a one-time-programmable memory architecture
US10156842B2 (en) 2015-12-31 2018-12-18 General Electric Company Device enrollment in a cloud service using an authenticated application
US9905315B1 (en) * 2017-01-24 2018-02-27 Nxp B.V. Error-resilient memory device with row and/or column folding with redundant resources and repair method thereof

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JPH0373495A (ja) * 1989-02-15 1991-03-28 Ricoh Co Ltd 半導体メモリ装置
US5146427A (en) * 1989-08-30 1992-09-08 Hitachi Ltd. High speed semiconductor memory having a direct-bypass signal path
JPH03156795A (ja) * 1989-11-15 1991-07-04 Toshiba Micro Electron Kk 半導体メモリ回路装置
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JP2530055B2 (ja) * 1990-08-30 1996-09-04 株式会社東芝 半導体集積回路
EP0491105B1 (en) * 1990-12-13 1996-05-01 STMicroelectronics S.r.l. Improved sense circuit for storage devices such as non-volatile memories, with enhanced sensing discrimination
IT1253678B (it) * 1991-07-31 1995-08-22 St Microelectronics Srl Architettura antirumore per memoria
US5677864A (en) * 1993-03-23 1997-10-14 Chung; David Siu Fu Intelligent memory architecture
US5555521A (en) * 1994-06-14 1996-09-10 Sanyo Electric Co., Ltd Method of operating the semiconductor memory storing analog data and analog data storing apparatus
KR0154193B1 (ko) * 1994-12-30 1998-12-01 김주용 센스 앰프회로
JP2643896B2 (ja) * 1995-02-23 1997-08-20 日本電気株式会社 半導体メモリ
US5561629A (en) * 1995-03-10 1996-10-01 Xilinx, Inc. Latching sense amplifier for a programmable logic device
JPH08273365A (ja) * 1995-03-31 1996-10-18 Nec Corp 半導体記憶装置
FR2734390B1 (fr) * 1995-05-19 1997-06-13 Sgs Thomson Microelectronics Circuit de detection de courant pour la lecture d'une memoire en circuit integre
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US5596539A (en) * 1995-12-28 1997-01-21 Lsi Logic Corporation Method and apparatus for a low power self-timed memory control system
US5608681A (en) * 1996-01-22 1997-03-04 Lsi Logic Corporation Fast memory sense system
EP0810607B1 (en) * 1996-05-17 2003-08-27 Hyundai Electronics America, Inc. Block write power reduction
US5751649A (en) * 1997-02-26 1998-05-12 Artisan Components, Inc. High speed memory output circuitry and methods for implementing same

Also Published As

Publication number Publication date
JP2001521262A (ja) 2001-11-06
WO1999022376A1 (en) 1999-05-06
US5999482A (en) 1999-12-07
EP1025565A4 (en) 2001-04-25
EP1025565B1 (en) 2003-06-04
EP1025565A1 (en) 2000-08-09
DE69815372D1 (de) 2003-07-10
DE69815372T2 (de) 2004-04-29
JP4209588B2 (ja) 2009-01-14

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase