IT1253678B - Architettura antirumore per memoria - Google Patents

Architettura antirumore per memoria

Info

Publication number
IT1253678B
IT1253678B ITVA910022A ITVA910022A IT1253678B IT 1253678 B IT1253678 B IT 1253678B IT VA910022 A ITVA910022 A IT VA910022A IT VA910022 A ITVA910022 A IT VA910022A IT 1253678 B IT1253678 B IT 1253678B
Authority
IT
Italy
Prior art keywords
memory
circuit
produced
input
signals
Prior art date
Application number
ITVA910022A
Other languages
English (en)
Inventor
Luigi Pascucci
Marco Olivo
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITVA910022A priority Critical patent/IT1253678B/it
Publication of ITVA910022A0 publication Critical patent/ITVA910022A0/it
Priority to US07/901,862 priority patent/US5404334A/en
Priority to DE69222249T priority patent/DE69222249T2/de
Priority to EP92830421A priority patent/EP0526433B1/en
Priority to JP22458792A priority patent/JP3479313B2/ja
Publication of ITVA910022A1 publication Critical patent/ITVA910022A1/it
Priority to US08/412,553 priority patent/US5844851A/en
Application granted granted Critical
Publication of IT1253678B publication Critical patent/IT1253678B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Una tipica memoria è resa sostanzialmente immune ai possibili effetti del rumore causato da transizioni sulle uscite che potrebbero causare erronee valutazioni e transizioni spurie sulle uscite provvedendo ad abilitare i circuiti di memorizzazione dei dati estratti (output latches) a cambiare di stato in funzione di un nuovo segnale di lettura prodotto per una qualsivoglia causa mediante un impulso di abilitazione di durata prestabilita il quale è prodotto solo a seguito di un'avvenuta transizione dei segnali di indirizzamento della memoria per un periodo di tempo di persistenza di detta transizione non inferiore al ritardo di propagazione dei segnali attraverso la memoria stessa. Ciò è ottenuto dotando la memoria di una rete antirumore costituita da un circuito rivelatore di transizioni dei segnali di indirizzamento della memoria gli impulsi prodotti dal quale sono applicati ad un primo ingresso di un circuito di reset ed all'ingresso di una catena circuitale dummy riproducente i ritardi di propagazione dei segnali attraverso la memoria costituita da gruppi circuitali individualmente abilitabili mediante il segnale di reset prodotto dall'apposito circuito. Un circuito generatore di impulsi singoli, è anch'esso abilitato dallo stesso segnale di reset e stimolato dai segnali propagati attraverso la catena circuitale dummy abilitata il quale produce l'impulso di abilitazione di durata prestabilita degli output latches il quale è anche applicato ad un secondo ingresso del circuito generatore del segnale di reset.
ITVA910022A 1991-07-31 1991-07-31 Architettura antirumore per memoria IT1253678B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
ITVA910022A IT1253678B (it) 1991-07-31 1991-07-31 Architettura antirumore per memoria
US07/901,862 US5404334A (en) 1991-07-31 1992-06-22 Anti-noise and auto-stand-by memory architecture
DE69222249T DE69222249T2 (de) 1991-07-31 1992-07-28 Anti-Rausch Speicherstruktur mit automatischem Wartezustand
EP92830421A EP0526433B1 (en) 1991-07-31 1992-07-28 Anti-noise and auto-stand-by memory architecture
JP22458792A JP3479313B2 (ja) 1991-07-31 1992-07-31 反ノイズ及び自動スタンバイメモリ構造
US08/412,553 US5844851A (en) 1991-07-31 1995-03-29 Anti-noise and auto-stand-by memory architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITVA910022A IT1253678B (it) 1991-07-31 1991-07-31 Architettura antirumore per memoria

Publications (3)

Publication Number Publication Date
ITVA910022A0 ITVA910022A0 (it) 1991-07-31
ITVA910022A1 ITVA910022A1 (it) 1993-01-31
IT1253678B true IT1253678B (it) 1995-08-22

Family

ID=11423142

Family Applications (1)

Application Number Title Priority Date Filing Date
ITVA910022A IT1253678B (it) 1991-07-31 1991-07-31 Architettura antirumore per memoria

Country Status (5)

Country Link
US (2) US5404334A (it)
EP (1) EP0526433B1 (it)
JP (1) JP3479313B2 (it)
DE (1) DE69222249T2 (it)
IT (1) IT1253678B (it)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1253678B (it) * 1991-07-31 1995-08-22 St Microelectronics Srl Architettura antirumore per memoria
JPH07220487A (ja) * 1994-01-27 1995-08-18 Toshiba Corp 不揮発性メモリ回路
EP0698884A1 (en) * 1994-08-24 1996-02-28 Advanced Micro Devices, Inc. Memory array for microprocessor cache
US5619466A (en) * 1996-01-19 1997-04-08 Sgs-Thomson Microelectronics, Inc. Low-power read circuit and method for controlling a sense amplifier
US5802004A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Clocked sense amplifier with wordline tracking
JPH09231770A (ja) * 1996-01-19 1997-09-05 Sgs Thomson Microelectron Inc メモリセルへの書込を終了させる回路及び方法
US5845059A (en) * 1996-01-19 1998-12-01 Stmicroelectronics, Inc. Data-input device for generating test signals on bit and bit-complement lines
US5883838A (en) * 1996-01-19 1999-03-16 Stmicroelectronics, Inc. Device and method for driving a conductive path with a signal
JPH09282886A (ja) * 1996-01-19 1997-10-31 Sgs Thomson Microelectron Inc メモリセルへの書込の開始をトラッキングする回路及び方法
US5691950A (en) * 1996-01-19 1997-11-25 Sgs-Thomson Microelectronics, Inc. Device and method for isolating bit lines from a data line
US5848018A (en) * 1996-01-19 1998-12-08 Stmicroelectronics, Inc. Memory-row selector having a test function
US5745432A (en) * 1996-01-19 1998-04-28 Sgs-Thomson Microelectronics, Inc. Write driver having a test function
US5864696A (en) * 1996-01-19 1999-01-26 Stmicroelectronics, Inc. Circuit and method for setting the time duration of a write to a memory cell
DE69630671D1 (de) * 1996-03-29 2003-12-18 St Microelectronics Srl Impulserzeugungsschaltung für synchrone Datenladung in einen Vorverstärkerpuffer, insbesonders für Speicheranordnungen
DE69631821D1 (de) * 1996-04-09 2004-04-15 St Microelectronics Srl Schaltung zur Bestimmung der vollständigen Aufladung einer generischen Bitleitung, insbesondere für nichtflüchtige Speicher
EP0805453B1 (en) * 1996-04-29 2004-01-02 STMicroelectronics S.r.l. Memory architecture for flexible reading management, particularly for non-volatile memories, having noise-immunity features, matching device performance, and having optimized throughput
JPH09320286A (ja) * 1996-05-24 1997-12-12 Nec Corp 半導体記憶装置
FR2755286B1 (fr) * 1996-10-25 1999-01-22 Sgs Thomson Microelectronics Memoire a temps de lecture ameliore
US6034908A (en) * 1997-02-11 2000-03-07 Artisan Components, Inc. Sense amplifying methods and sense amplification integrated devices
AU6154498A (en) * 1997-02-11 1998-08-26 Artisan Components, Inc. Sense amplifying methods and sense amplification and output buffer integrated circuits
US5717633A (en) * 1997-02-11 1998-02-10 Artisan Components, Inc. Low power consuming memory sense amplifying circuitry
US5886929A (en) * 1997-04-21 1999-03-23 Artisan Components, Inc. High speed addressing buffer and methods for implementing same
US5889715A (en) * 1997-04-23 1999-03-30 Artisan Components, Inc. Voltage sense amplifier and methods for implementing the same
US5917768A (en) * 1997-04-24 1999-06-29 Sgs-Thomson Microelectronics S.R.L. Memory architecture for flexible reading management, particularly for non-volatile memories, having noise-immunity features, matching device performance, and having optimized throughout
US5881008A (en) * 1997-09-12 1999-03-09 Artisan Components, Inc. Self adjusting pre-charge delay in memory circuits and methods for making the same
US5883854A (en) * 1997-09-12 1999-03-16 Artisan Components, Inc. Distributed balanced address detection and clock buffer circuitry and methods for making the same
US5965925A (en) * 1997-10-22 1999-10-12 Artisan Components, Inc. Integrated circuit layout methods and layout structures
US5999482A (en) * 1997-10-24 1999-12-07 Artisan Components, Inc. High speed memory self-timing circuitry and methods for implementing the same
WO1999022377A1 (en) * 1997-10-25 1999-05-06 Artisan Components, Inc. Low power differential signal transition techniques for use in memory devices
EP0915477B1 (en) * 1997-11-05 2004-03-17 STMicroelectronics S.r.l. Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory
US6016390A (en) * 1998-01-29 2000-01-18 Artisan Components, Inc. Method and apparatus for eliminating bitline voltage offsets in memory devices
IT1301879B1 (it) * 1998-07-30 2000-07-07 St Microelectronics Srl Circuiteria a generatore di impulsi per temporizzare un dispositivodi memoria a basso consumo
US5946255A (en) * 1998-07-31 1999-08-31 Cypress Semiconductor Corp. Wordline synchronized reference voltage generator
US6282127B1 (en) 1999-02-03 2001-08-28 Xilinx, Inc. Block RAM with reset to user selected value
US6101132A (en) * 1999-02-03 2000-08-08 Xilinx, Inc. Block RAM with reset
JP3825596B2 (ja) * 1999-11-12 2006-09-27 株式会社東芝 半導体記憶装置及びその制御方法
US6438040B1 (en) * 2000-07-31 2002-08-20 Stmicroelectronics S.R.L. Enabling circuit for output devices in electronic memories
US7184328B2 (en) 2004-10-18 2007-02-27 Infineon Technologies Ag DQS for data from a memory array
US8811109B2 (en) 2012-02-27 2014-08-19 Qualcomm Incorporated Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6032911B2 (ja) * 1979-07-26 1985-07-31 株式会社東芝 半導体記憶装置
JPS58169383A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 半導体記憶装置
JPS5952492A (ja) * 1982-09-17 1984-03-27 Fujitsu Ltd スタテイツク型半導体記憶装置
JPS62180607A (ja) * 1986-02-04 1987-08-07 Fujitsu Ltd 半導体集積回路
US4953130A (en) * 1988-06-27 1990-08-28 Texas Instruments, Incorporated Memory circuit with extended valid data output time
JPH02161686A (ja) * 1988-12-13 1990-06-21 Oki Electric Ind Co Ltd Ｍｏｓ型半導体記憶装置
JPH0373495A (ja) * 1989-02-15 1991-03-28 Ricoh Co Ltd 半導体メモリ装置
IT1253678B (it) * 1991-07-31 1995-08-22 St Microelectronics Srl Architettura antirumore per memoria

Also Published As

Publication number Publication date
DE69222249T2 (de) 1998-04-02
US5844851A (en) 1998-12-01
JPH06342596A (ja) 1994-12-13
ITVA910022A1 (it) 1993-01-31
US5404334A (en) 1995-04-04
EP0526433B1 (en) 1997-09-17
DE69222249D1 (de) 1997-10-23
ITVA910022A0 (it) 1991-07-31
EP0526433A3 (en) 1993-08-04
JP3479313B2 (ja) 2003-12-15
EP0526433A2 (en) 1993-02-03

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970730