JP4159887B2 - 重ね合わせ検査工程を備えた半導体装置の製造方法 - Google Patents

重ね合わせ検査工程を備えた半導体装置の製造方法 Download PDF

Info

Publication number
JP4159887B2
JP4159887B2 JP2003004744A JP2003004744A JP4159887B2 JP 4159887 B2 JP4159887 B2 JP 4159887B2 JP 2003004744 A JP2003004744 A JP 2003004744A JP 2003004744 A JP2003004744 A JP 2003004744A JP 4159887 B2 JP4159887 B2 JP 4159887B2
Authority
JP
Japan
Prior art keywords
overlay
resist film
mark
layer
overlay mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003004744A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004221194A (ja
JP2004221194A5 (enExample
Inventor
健 岸田
成範 城戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2003004744A priority Critical patent/JP4159887B2/ja
Priority to US10/437,911 priority patent/US6775920B2/en
Priority to TW092116049A priority patent/TWI222693B/zh
Priority to KR1020030044511A priority patent/KR100572736B1/ko
Publication of JP2004221194A publication Critical patent/JP2004221194A/ja
Publication of JP2004221194A5 publication Critical patent/JP2004221194A5/ja
Application granted granted Critical
Publication of JP4159887B2 publication Critical patent/JP4159887B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2003004744A 2003-01-10 2003-01-10 重ね合わせ検査工程を備えた半導体装置の製造方法 Expired - Fee Related JP4159887B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003004744A JP4159887B2 (ja) 2003-01-10 2003-01-10 重ね合わせ検査工程を備えた半導体装置の製造方法
US10/437,911 US6775920B2 (en) 2003-01-10 2003-05-15 Method of fabricating semiconductor device comprising superposition inspection step
TW092116049A TWI222693B (en) 2003-01-10 2003-06-13 Method of fabricating semiconductor device comprising superposition inspection step
KR1020030044511A KR100572736B1 (ko) 2003-01-10 2003-07-02 중첩검사공정을 구비한 반도체장치의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003004744A JP4159887B2 (ja) 2003-01-10 2003-01-10 重ね合わせ検査工程を備えた半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2004221194A JP2004221194A (ja) 2004-08-05
JP2004221194A5 JP2004221194A5 (enExample) 2005-12-15
JP4159887B2 true JP4159887B2 (ja) 2008-10-01

Family

ID=32708975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003004744A Expired - Fee Related JP4159887B2 (ja) 2003-01-10 2003-01-10 重ね合わせ検査工程を備えた半導体装置の製造方法

Country Status (4)

Country Link
US (1) US6775920B2 (enExample)
JP (1) JP4159887B2 (enExample)
KR (1) KR100572736B1 (enExample)
TW (1) TWI222693B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007049074A (ja) * 2005-08-12 2007-02-22 Oki Electric Ind Co Ltd 合わせ誤差計測マークおよびこれを用いた半導体装置の製造方法
CN113534604B (zh) * 2020-03-31 2023-11-24 长鑫存储技术有限公司 标记检测方法、装置及计算机可读存储介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05121284A (ja) 1991-10-11 1993-05-18 Meidensha Corp 半導体装置の製造方法
JPH08298236A (ja) 1995-04-26 1996-11-12 Sony Corp パターンの露光方法及びその装置
JPH09266235A (ja) 1996-03-28 1997-10-07 Sony Corp 不良解析方法とそのシステム
JP4680424B2 (ja) * 2001-06-01 2011-05-11 Ｏｋｉセミコンダクタ株式会社 重ね合わせ位置検出マークの製造方法

Also Published As

Publication number Publication date
KR100572736B1 (ko) 2006-04-25
JP2004221194A (ja) 2004-08-05
KR20040064583A (ko) 2004-07-19
TW200412640A (en) 2004-07-16
TWI222693B (en) 2004-10-21
US6775920B2 (en) 2004-08-17
US20040137649A1 (en) 2004-07-15

Similar Documents

Publication Publication Date Title
JP4528464B2 (ja) アライメント方法、重ね合わせ検査方法及びフォトマスク
JP4537124B2 (ja) オーバーレイキー、アラインキーを有する集積回路半導体素子およびその製造方法
JP2009238777A (ja) 半導体装置の製造方法
US8241988B2 (en) Photo key and method of fabricating semiconductor device using the photo key
US8502355B2 (en) Overlay vernier mask pattern, formation method thereof, semiconductor device including overlay vernier pattern, and formation method thereof
JP4680424B2 (ja) 重ね合わせ位置検出マークの製造方法
JP4159887B2 (ja) 重ね合わせ検査工程を備えた半導体装置の製造方法
US7952213B2 (en) Overlay mark arrangement for reducing overlay shift
TWI581055B (zh) 形成光罩的方法
US20080061338A1 (en) Method for Processing a Structure of a Semiconductor Component, and Structure in a Semiconductor Component
JP4397248B2 (ja) 半導体装置及びその製造方法
US7595258B2 (en) Overlay vernier of semiconductor device and method of manufacturing the same
US7999399B2 (en) Overlay vernier key and method for fabricating the same
JP2004214670A (ja) 半導体素子のキー整列方法
US12463144B2 (en) Overlay metrology mark
JP2010080625A (ja) マスクパターンの形成方法および半導体装置の製造方法
JP2006140300A (ja) 半導体装置、ウェーハ及び半導体装置の製造方法
JP2002025888A (ja) アライメントマークおよびその形成方法、並びに半導体装置の製造方法
JP3583044B2 (ja) 半導体装置及びアライメントずれの制御方法
JP2975871B2 (ja) 合わせマークの位置ずれ検査方法
JP2748029B2 (ja) 位置合わせマーク作成方法
US20090111059A1 (en) Patterning Method of Semiconductor Device
JP2006229132A (ja) レジストパターン形成方法
JP2004319637A (ja) アライメントマークの形成方法およびそれを用いた半導体装置の製造方法
CN116844954A (zh) 形成半导体元件图案的方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051028

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051028

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070619

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070626

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070827

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080708

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080716

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110725

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110725

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110725

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120725

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120725

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130725

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees