TWI222693B - Method of fabricating semiconductor device comprising superposition inspection step - Google Patents
Method of fabricating semiconductor device comprising superposition inspection step Download PDFInfo
- Publication number
- TWI222693B TWI222693B TW092116049A TW92116049A TWI222693B TW I222693 B TWI222693 B TW I222693B TW 092116049 A TW092116049 A TW 092116049A TW 92116049 A TW92116049 A TW 92116049A TW I222693 B TWI222693 B TW I222693B
- Authority
- TW
- Taiwan
- Prior art keywords
- photoresist film
- mark
- overlap
- information
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003004744A JP4159887B2 (ja) | 2003-01-10 | 2003-01-10 | 重ね合わせ検査工程を備えた半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200412640A TW200412640A (en) | 2004-07-16 |
| TWI222693B true TWI222693B (en) | 2004-10-21 |
Family
ID=32708975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092116049A TWI222693B (en) | 2003-01-10 | 2003-06-13 | Method of fabricating semiconductor device comprising superposition inspection step |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6775920B2 (enExample) |
| JP (1) | JP4159887B2 (enExample) |
| KR (1) | KR100572736B1 (enExample) |
| TW (1) | TWI222693B (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007049074A (ja) * | 2005-08-12 | 2007-02-22 | Oki Electric Ind Co Ltd | 合わせ誤差計測マークおよびこれを用いた半導体装置の製造方法 |
| CN113534604B (zh) * | 2020-03-31 | 2023-11-24 | 长鑫存储技术有限公司 | 标记检测方法、装置及计算机可读存储介质 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121284A (ja) | 1991-10-11 | 1993-05-18 | Meidensha Corp | 半導体装置の製造方法 |
| JPH08298236A (ja) | 1995-04-26 | 1996-11-12 | Sony Corp | パターンの露光方法及びその装置 |
| JPH09266235A (ja) | 1996-03-28 | 1997-10-07 | Sony Corp | 不良解析方法とそのシステム |
| JP4680424B2 (ja) * | 2001-06-01 | 2011-05-11 | Okiセミコンダクタ株式会社 | 重ね合わせ位置検出マークの製造方法 |
-
2003
- 2003-01-10 JP JP2003004744A patent/JP4159887B2/ja not_active Expired - Fee Related
- 2003-05-15 US US10/437,911 patent/US6775920B2/en not_active Expired - Fee Related
- 2003-06-13 TW TW092116049A patent/TWI222693B/zh active
- 2003-07-02 KR KR1020030044511A patent/KR100572736B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR100572736B1 (ko) | 2006-04-25 |
| JP2004221194A (ja) | 2004-08-05 |
| KR20040064583A (ko) | 2004-07-19 |
| TW200412640A (en) | 2004-07-16 |
| US6775920B2 (en) | 2004-08-17 |
| US20040137649A1 (en) | 2004-07-15 |
| JP4159887B2 (ja) | 2008-10-01 |
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