JP4145879B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
- Publication number
- JP4145879B2 JP4145879B2 JP2004572090A JP2004572090A JP4145879B2 JP 4145879 B2 JP4145879 B2 JP 4145879B2 JP 2004572090 A JP2004572090 A JP 2004572090A JP 2004572090 A JP2004572090 A JP 2004572090A JP 4145879 B2 JP4145879 B2 JP 4145879B2
- Authority
- JP
- Japan
- Prior art keywords
- flexible tape
- semiconductor package
- mounting portion
- package according
- speed signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 64
- 230000005540 biological transmission Effects 0.000 claims description 26
- 239000003351 stiffener Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 claims description 5
- 230000005855 radiation Effects 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 230000006866 deterioration Effects 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10439—Position of a single component
- H05K2201/10492—Electrically connected to another device
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
Claims (16)
- 実装部分及び延長部分を有するフレキシブルテープと、
該フレキシブルテープの前記実装部分に設けられた複数のアレイ状接続電極と、
前記フレキシブルテープの前記実装部分に搭載された半導体チップと、
前記フレキシブルテープの前記延長部分の先端に形成されたメタルリードの高速信号用電極と、
前記半導体チップと前記高速信号用電極を接続する前記フレキシブルテープに設けられた伝送線路と、
を具備したことを特徴とする半導体パッケージ。 - 前記フレキシブルテープの前記実装部分に搭載されたスティフナを更に具備した請求項1記載の半導体パッケージ。
- 前記スティフナはセラミックから形成されており、前記フレキシブルテープの前記実装部分に接着されている請求項2記載の半導体パッケージ。
- 前記スティフナは樹脂から形成されており、前記フレキシブルテープの前記実装部分に接着されている請求項2記載の半導体パッケージ。
- 前記延長部分は前記実装部分の幅より狭い幅を有している請求項1記載の半導体パッケージ。
- 実装部分及び延長部分を有するフレキシブルテープと、
該フレキシブルテープの前記実装部分に設けられた複数のアレイ状接続電極と、
前記フレキシブルテープの前記実装部分に搭載された半導体チップと、
前記フレキシブルテープの前記延長部分の先端に形成された高速信号用電極と、
前記半導体チップと前記高速信号用電極を接続する前記フレキシブルテープに設けられた伝送線路とを具備し、
前記スティフナはセラミックから形成されており、前記フレキシブルテープの前記実装部分に接着され、前記高速信号用電極を間に挟んで前記フレキシブルテープの前記延長部分の先端に形成された一対のグランド電極を更に具備した半導体パッケージ。 - 前記フレキシブルテープは前記伝送線路の両側に第1グランドパターンを有しており、前記各グランド電極は該第1グランドパターンに接続されている請求項6記載の半導体パッケージ。
- 前記フレキシブルテープは前記伝送線路が形成された面と反対側の面の少なくとも前記伝送線路及び前記第1グランドパターンに対応する部分に第2グランドパターンを有している請求項7記載の半導体パッケージ。
- 前記半導体チップは前記フレキシブルテープの実装部分にフリップチップボンディングされている請求項2記載の半導体パッケージ。
- 前記半導体チップは前記フレキシブルテープの前記実装部分にTAB接続されている請求項2記載の半導体パッケージ。
- 前記フレキシブルテープが実装されるプリント配線板を更に具備し、
前記複数のアレイ状接続電極と前記プリント配線板はボールグリッドアレイにより接続されている請求項6記載の半導体パッケージ。 - 前記プリント配線板は前記伝送線路とインピーダンス整合された配線パターンと、グランドパターンを有しており、前記高速信号用電極は前記配線パターンに接続され、前記グランド電極は前記グランドパターンに接続されている請求項11記載の半導体パッケージ。
- 前記高速信号用電極に接続されたコネクタを更に具備した請求項11記載の半導体パッケージ。
- 高速信号用電極に接続された高周波部品を更に具備した請求項11記載の半導体パッケージ。
- 前記プリント配線板及び前記高周波部品が搭載される金属ブロックを更に具備し、
該金属ブロックは該金属ブロック上に搭載された前記高周波部品の高さが前記プリント配線板より高くなるような段差を有している請求項14記載の半導体パッケージ。 - 前記スティフナ上に搭載された放熱フィンを更に具備した請求項2記載の半導体パッケージ。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/006259 WO2004105128A1 (ja) | 2003-05-20 | 2003-05-20 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2004105128A1 JPWO2004105128A1 (ja) | 2006-07-20 |
JP4145879B2 true JP4145879B2 (ja) | 2008-09-03 |
Family
ID=33463125
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004572090A Expired - Fee Related JP4145879B2 (ja) | 2003-05-20 | 2003-05-20 | 半導体パッケージ |
Country Status (3)
Country | Link |
---|---|
US (1) | US7279778B2 (ja) |
JP (1) | JP4145879B2 (ja) |
WO (1) | WO2004105128A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090065954A1 (en) * | 2007-09-07 | 2009-03-12 | Attma Sharma | Packaging Method For Wideband Power Using Transmission Lines |
JP2011134789A (ja) * | 2009-12-22 | 2011-07-07 | Mitsubishi Electric Corp | 半導体装置、及びプリント配線板 |
JP2014067755A (ja) * | 2012-09-24 | 2014-04-17 | Renesas Electronics Corp | 半導体装置、半導体装置の設計方法、及び半導体装置の製造方法 |
FR3000325B1 (fr) * | 2012-12-21 | 2016-04-29 | Thales Sa | Dispositif d'interconnexion pour circuits electroniques, notamment des circuits electroniques hyperfrequence |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0982877A (ja) * | 1995-09-19 | 1997-03-28 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置及びそれに用いられるリードフレーム部材 |
JP3942206B2 (ja) * | 1995-12-25 | 2007-07-11 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US5760465A (en) * | 1996-02-01 | 1998-06-02 | International Business Machines Corporation | Electronic package with strain relief means |
JPH09232368A (ja) * | 1996-02-20 | 1997-09-05 | Fujitsu Ltd | 半導体装置 |
JP2882396B2 (ja) | 1997-03-24 | 1999-04-12 | 日本電気株式会社 | 半導体装置 |
US6194669B1 (en) | 1999-02-05 | 2001-02-27 | Trw Inc. | Solder ball grid array for connecting multiple millimeter wave assemblies |
JP3239874B2 (ja) * | 1999-02-19 | 2001-12-17 | 日本電気株式会社 | 半導体装置 |
JP2001077236A (ja) * | 1999-09-07 | 2001-03-23 | Casio Comput Co Ltd | 半導体装置及びその接合構造 |
JP2002016167A (ja) * | 2000-06-28 | 2002-01-18 | Kyocera Corp | 半導体素子収納用パッケージ部品及びこれを用いた半導体素子収納用パッケージ |
AU2002217987A1 (en) * | 2000-12-01 | 2002-06-11 | Broadcom Corporation | Thermally and electrically enhanced ball grid array packaging |
-
2003
- 2003-05-20 WO PCT/JP2003/006259 patent/WO2004105128A1/ja active Application Filing
- 2003-05-20 JP JP2004572090A patent/JP4145879B2/ja not_active Expired - Fee Related
-
2005
- 2005-06-03 US US11/143,641 patent/US7279778B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPWO2004105128A1 (ja) | 2006-07-20 |
US7279778B2 (en) | 2007-10-09 |
WO2004105128A1 (ja) | 2004-12-02 |
US20050224929A1 (en) | 2005-10-13 |
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